1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Microchip LAN966x SoC Clock driver.
11 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/microchip,lan966x.h>
69 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_enable()  local
70 	u32 val = readl(gck->reg);  in lan966x_gck_enable()
73 	writel(val, gck->reg);  in lan966x_gck_enable()
80 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_disable()  local
81 	u32 val = readl(gck->reg);  in lan966x_gck_disable()
84 	writel(val, gck->reg);  in lan966x_gck_disable()
91 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_set_rate()  local
92 	u32 div, val = readl(gck->reg);  in lan966x_gck_set_rate()
95 		return -EINVAL;  in lan966x_gck_set_rate()
100 	val |= FIELD_PREP(GCK_PRESCALER, (div - 1));  in lan966x_gck_set_rate()
101 	writel(val, gck->reg);  in lan966x_gck_set_rate()
109 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_recalc_rate()  local
110 	u32 div, val = readl(gck->reg);  in lan966x_gck_recalc_rate()
128 		/* Allowed prescaler divider range is 0-255 */  in lan966x_gck_determine_rate()
129 		if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {  in lan966x_gck_determine_rate()
130 			req->best_parent_hw = parent;  in lan966x_gck_determine_rate()
131 			req->best_parent_rate = clk_hw_get_rate(parent);  in lan966x_gck_determine_rate()
137 	return -EINVAL;  in lan966x_gck_determine_rate()
142 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_get_parent()  local
143 	u32 val = readl(gck->reg);  in lan966x_gck_get_parent()
150 	struct lan966x_gck *gck = to_lan966x_gck(hw);  in lan966x_gck_set_parent()  local
151 	u32 val = readl(gck->reg);  in lan966x_gck_set_parent()
155 	writel(val, gck->reg);  in lan966x_gck_set_parent()
177 		return ERR_PTR(-ENOMEM);  in lan966x_gck_clk_register()
179 	priv->reg = base + (i * 4);  in lan966x_gck_clk_register()
180 	priv->hw.init = &init;  in lan966x_gck_clk_register()
181 	ret = devm_clk_hw_register(dev, &priv->hw);  in lan966x_gck_clk_register()
185 	return &priv->hw;  in lan966x_gck_clk_register()
195 		int idx = i - GCK_GATE_UHPHS;  in lan966x_gate_clk_register()
197 		hw_data->hws[i] =  in lan966x_gate_clk_register()
199 						  "lan966x", 0, gate_base,  in lan966x_gate_clk_register()
203 		if (IS_ERR(hw_data->hws[i]))  in lan966x_gate_clk_register()
204 			return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),  in lan966x_gate_clk_register()
215 	struct device *dev = &pdev->dev;  in lan966x_clk_probe()
223 		return -ENOMEM;  in lan966x_clk_probe()
231 	hw_data->num = GCK_GATE_UHPHS;  in lan966x_clk_probe()
235 		hw_data->hws[i] = lan966x_gck_clk_register(dev, i);  in lan966x_clk_probe()
236 		if (IS_ERR(hw_data->hws[i])) {  in lan966x_clk_probe()
239 			return PTR_ERR(hw_data->hws[i]);  in lan966x_clk_probe()
245 		gate_base = devm_ioremap_resource(&pdev->dev, res);  in lan966x_clk_probe()
249 		hw_data->num = N_CLOCKS;  in lan966x_clk_probe()
260 	{ .compatible = "microchip,lan966x-gck", },
268 		.name = "lan966x-clk",
275 MODULE_DESCRIPTION("LAN966X clock driver");