39 	void __iomem	*reg;  member
46 	u32 reg;  in clk_pll_prepare()  local
48 	reg = readl(hbclk->reg);  in clk_pll_prepare()
49 	reg &= ~HB_PLL_RESET;  in clk_pll_prepare()
50 	writel(reg, hbclk->reg);  in clk_pll_prepare()
52 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_prepare()
54 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_prepare()
63 	u32 reg;  in clk_pll_unprepare()  local
65 	reg = readl(hbclk->reg);  in clk_pll_unprepare()
66 	reg |= HB_PLL_RESET;  in clk_pll_unprepare()
67 	writel(reg, hbclk->reg);  in clk_pll_unprepare()
73 	u32 reg;  in clk_pll_enable()  local
75 	reg = readl(hbclk->reg);  in clk_pll_enable()
76 	reg |= HB_PLL_EXT_ENA;  in clk_pll_enable()
77 	writel(reg, hbclk->reg);  in clk_pll_enable()
85 	u32 reg;  in clk_pll_disable()  local
87 	reg = readl(hbclk->reg);  in clk_pll_disable()
88 	reg &= ~HB_PLL_EXT_ENA;  in clk_pll_disable()
89 	writel(reg, hbclk->reg);  in clk_pll_disable()
96 	unsigned long divf, divq, vco_freq, reg;  in clk_pll_recalc_rate()  local
98 	reg = readl(hbclk->reg);  in clk_pll_recalc_rate()
99 	if (reg & HB_PLL_EXT_BYPASS)  in clk_pll_recalc_rate()
102 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;  in clk_pll_recalc_rate()
103 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
149 	u32 reg;  in clk_pll_set_rate()  local
153 	reg = readl(hbclk->reg);  in clk_pll_set_rate()
154 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {  in clk_pll_set_rate()
156 		reg |= HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
157 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
159 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
160 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);  in clk_pll_set_rate()
161 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);  in clk_pll_set_rate()
162 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
163 		writel(reg, hbclk->reg);  in clk_pll_set_rate()
165 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_set_rate()
167 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_set_rate()
169 		reg |= HB_PLL_EXT_ENA;  in clk_pll_set_rate()
170 		reg &= ~HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
172 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
173 		reg &= ~HB_PLL_DIVQ_MASK;  in clk_pll_set_rate()
174 		reg |= divq << HB_PLL_DIVQ_SHIFT;  in clk_pll_set_rate()
175 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
177 	writel(reg, hbclk->reg);  in clk_pll_set_rate()
196 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;  in clk_cpu_periphclk_recalc_rate()
208 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;  in clk_cpu_a9bclk_recalc_rate()
223 	div = readl(hbclk->reg) & 0x1f;  in clk_periclk_recalc_rate()
252 	writel(div >> 1, hbclk->reg);  in clk_periclk_set_rate()
264 	u32 reg;  in hb_clk_init()  local
272 	rc = of_property_read_u32(node, "reg", &reg);  in hb_clk_init()
282 	hb_clk->reg = of_iomap(srnp, 0);  in hb_clk_init()
284 	BUG_ON(!hb_clk->reg);  in hb_clk_init()
285 	hb_clk->reg += reg;  in hb_clk_init()