1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 #include <linux/clk-provider.h>
21  * prepare - clk_(un)prepare only ensures parent is (un)prepared
22  * enable - clk_enable and clk_disable are functional & control gating
23  * rate - inherits rate from parent.  No clk_set_rate support
24  * parent - fixed parent.  No clk_set_parent support
29 	if (gate->flags & CLK_GATE_BIG_ENDIAN)  in clk_gate_readl()
30 		return ioread32be(gate->reg);  in clk_gate_readl()
32 	return readl(gate->reg);  in clk_gate_readl()
37 	if (gate->flags & CLK_GATE_BIG_ENDIAN)  in clk_gate_writel()
38 		iowrite32be(val, gate->reg);  in clk_gate_writel()
40 		writel(val, gate->reg);  in clk_gate_writel()
47  *	set2dis = 1	-> clear bit	-> set = 0
48  *	set2dis = 0	-> set bit	-> set = 1
51  *	set2dis = 1	-> set bit	-> set = 1
52  *	set2dis = 0	-> clear bit	-> set = 0
59 	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;  in clk_gate_endisable()
61 	u32 reg;  in clk_gate_endisable()  local
65 	if (gate->lock)  in clk_gate_endisable()
66 		spin_lock_irqsave(gate->lock, flags);  in clk_gate_endisable()
68 		__acquire(gate->lock);  in clk_gate_endisable()
70 	if (gate->flags & CLK_GATE_HIWORD_MASK) {  in clk_gate_endisable()
71 		reg = BIT(gate->bit_idx + 16);  in clk_gate_endisable()
73 			reg |= BIT(gate->bit_idx);  in clk_gate_endisable()
75 		reg = clk_gate_readl(gate);  in clk_gate_endisable()
78 			reg |= BIT(gate->bit_idx);  in clk_gate_endisable()
80 			reg &= ~BIT(gate->bit_idx);  in clk_gate_endisable()
83 	clk_gate_writel(gate, reg);  in clk_gate_endisable()
85 	if (gate->lock)  in clk_gate_endisable()
86 		spin_unlock_irqrestore(gate->lock, flags);  in clk_gate_endisable()
88 		__release(gate->lock);  in clk_gate_endisable()
105 	u32 reg;  in clk_gate_is_enabled()  local
108 	reg = clk_gate_readl(gate);  in clk_gate_is_enabled()
111 	if (gate->flags & CLK_GATE_SET_TO_DISABLE)  in clk_gate_is_enabled()
112 		reg ^= BIT(gate->bit_idx);  in clk_gate_is_enabled()
114 	reg &= BIT(gate->bit_idx);  in clk_gate_is_enabled()
116 	return reg ? 1 : 0;  in clk_gate_is_enabled()
132 		void __iomem *reg, u8 bit_idx,  in __clk_hw_register_gate()  argument
137 	struct clk_init_data init = {};  in __clk_hw_register_gate()  local
138 	int ret = -EINVAL;  in __clk_hw_register_gate()
143 			return ERR_PTR(-EINVAL);  in __clk_hw_register_gate()
150 		return ERR_PTR(-ENOMEM);  in __clk_hw_register_gate()
152 	init.name = name;  in __clk_hw_register_gate()
153 	init.ops = &clk_gate_ops;  in __clk_hw_register_gate()
154 	init.flags = flags;  in __clk_hw_register_gate()
155 	init.parent_names = parent_name ? &parent_name : NULL;  in __clk_hw_register_gate()
156 	init.parent_hws = parent_hw ? &parent_hw : NULL;  in __clk_hw_register_gate()
157 	init.parent_data = parent_data;  in __clk_hw_register_gate()
159 		init.num_parents = 1;  in __clk_hw_register_gate()
161 		init.num_parents = 0;  in __clk_hw_register_gate()
164 	gate->reg = reg;  in __clk_hw_register_gate()
165 	gate->bit_idx = bit_idx;  in __clk_hw_register_gate()
166 	gate->flags = clk_gate_flags;  in __clk_hw_register_gate()
167 	gate->lock = lock;  in __clk_hw_register_gate()
168 	gate->hw.init = &init;  in __clk_hw_register_gate()
170 	hw = &gate->hw;  in __clk_hw_register_gate()
187 		void __iomem *reg, u8 bit_idx,  in clk_register_gate()  argument
192 	hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,  in clk_register_gate()
196 	return hw->clk;  in clk_register_gate()
237 		void __iomem *reg, u8 bit_idx,  in __devm_clk_hw_register_gate()  argument
244 		return ERR_PTR(-ENOMEM);  in __devm_clk_hw_register_gate()
247 				    parent_data, flags, reg, bit_idx,  in __devm_clk_hw_register_gate()