1 // SPDX-License-Identifier: GPL-2.0-only
3  * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22  * struct axxia_clk - Common struct to all Axxia clocks.
33  * struct axxia_pllclk - Axxia PLL generated clock.
35  * @reg: Offset into regmap for PLL control register
39 	u32 reg;  member
44  * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 	regmap_read(aclk->regmap, pll->reg, &control);  in axxia_pllclk_recalc()
69  * struct axxia_divclk - Axxia clock divider
71  * @reg: Offset into regmap for PLL control register
77 	u32 reg;  member
84  * axxia_divclk_recalc_rate - Calculate clock divider output rage
93 	regmap_read(aclk->regmap, divclk->reg, &ctrl);  in axxia_divclk_recalc_rate()
94 	div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1));  in axxia_divclk_recalc_rate()
104  * struct axxia_clkmux - Axxia clock mux
106  * @reg: Offset into regmap for PLL control register
112 	u32 reg;  member
119  * axxia_clkmux_get_parent - Return the index of selected parent clock
127 	regmap_read(aclk->regmap, mux->reg, &ctrl);  in axxia_clkmux_get_parent()
128 	parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1);  in axxia_clkmux_get_parent()
143 	.aclk.hw.init = &(struct clk_init_data){
151 	.reg   = 0x01800,
155 	.aclk.hw.init = &(struct clk_init_data){
163 	.reg   = 0x02000,
167 	.aclk.hw.init = &(struct clk_init_data){
175 	.reg   = 0x02800,
179 	.aclk.hw.init = &(struct clk_init_data){
187 	.reg   = 0x03000,
191 	.aclk.hw.init = &(struct clk_init_data){
199 	.reg   = 0x03800,
207 	.aclk.hw.init = &(struct clk_init_data){
215 	.reg   = 0x10008,
221 	.aclk.hw.init = &(struct clk_init_data){
229 	.reg   = 0x10008,
235 	.aclk.hw.init = &(struct clk_init_data){
243 	.reg   = 0x10008,
249 	.aclk.hw.init = &(struct clk_init_data){
257 	.reg   = 0x10008,
263 	.aclk.hw.init = &(struct clk_init_data){
271 	.reg   = 0x1000c,
277 	.aclk.hw.init = &(struct clk_init_data){
285 	.reg   = 0x1000c,
291 	.aclk.hw.init = &(struct clk_init_data){
299 	.reg   = 0x1000c,
305 	.aclk.hw.init = &(struct clk_init_data){
313 	.reg   = 0x1000c,
319 	.aclk.hw.init = &(struct clk_init_data){
327 	.reg   = 0x1000c,
337 	.aclk.hw.init = &(struct clk_init_data){
348 	.reg   = 0x10000,
354 	.aclk.hw.init = &(struct clk_init_data){
365 	.reg   = 0x10000,
371 	.aclk.hw.init = &(struct clk_init_data){
382 	.reg   = 0x10000,
388 	.aclk.hw.init = &(struct clk_init_data){
399 	.reg   = 0x10000,
405 	.aclk.hw.init = &(struct clk_init_data){
416 	.reg   = 0x10004,
422 	.aclk.hw.init = &(struct clk_init_data){
433 	.reg   = 0x10004,
439 	.aclk.hw.init = &(struct clk_init_data){
450 	.reg   = 0x10004,
456 	.aclk.hw.init = &(struct clk_init_data){
465 	.reg   = 0x10004,
471 	.aclk.hw.init = &(struct clk_init_data){
480 	.reg   = 0x10004,
517 	unsigned int idx = clkspec->args[0];  in of_clk_axmclk_get()
521 		return ERR_PTR(-EINVAL);  in of_clk_axmclk_get()
524 	return &axmclk_clocks[idx]->hw;  in of_clk_axmclk_get()
536 	{ .compatible = "lsi,axm5516-clks" },
545 	struct device *dev = &pdev->dev;  in axmclk_probe()
564 		axmclk_clocks[i]->regmap = regmap;  in axmclk_probe()
565 		ret = devm_clk_hw_register(dev, &axmclk_clocks[i]->hw);  in axmclk_probe()
576 		.name	= "clk-axm5516",
595 MODULE_ALIAS("platform:clk-axm5516");