clk/bcm/clk-sr.c

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 		.channel = BCM_SR_GENPLL0_125M_CLK,
52 		.mdiv = REG_VAL(0x18, 0, 9),
55 		.channel = BCM_SR_GENPLL0_SCR_CLK,
58 		.mdiv = REG_VAL(0x18, 10, 9),
61 		.channel = BCM_SR_GENPLL0_250M_CLK,
64 		.mdiv = REG_VAL(0x18, 20, 9),
67 		.channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
69 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
70 		.mdiv = REG_VAL(0x1c, 0, 9),
73 		.channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
76 		.mdiv = REG_VAL(0x1c, 10, 9),
79 		.channel = BCM_SR_GENPLL0_PAXC_AXI_CLK,
82 		.mdiv = REG_VAL(0x1c, 20, 9),
88 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll0_clk_init()
109 		.channel = BCM_SR_GENPLL2_NIC_CLK,
112 		.mdiv = REG_VAL(0x18, 0, 9),
115 		.channel = BCM_SR_GENPLL2_TS_500_CLK,
118 		.mdiv = REG_VAL(0x18, 10, 9),
121 		.channel = BCM_SR_GENPLL2_125_NITRO_CLK,
124 		.mdiv = REG_VAL(0x18, 20, 9),
127 		.channel = BCM_SR_GENPLL2_CHIMP_CLK,
129 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
130 		.mdiv = REG_VAL(0x1c, 0, 9),
133 		.channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
136 		.mdiv = REG_VAL(0x1c, 10, 9),
139 		.channel = BCM_SR_GENPLL2_FS4_CLK,
141 		.mdiv = REG_VAL(0x1c, 20, 9),
147 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll2_clk_init()
168 		.channel = BCM_SR_GENPLL3_HSLS_CLK,
171 		.mdiv = REG_VAL(0x18, 0, 9),
174 		.channel = BCM_SR_GENPLL3_SDIO_CLK,
177 		.mdiv = REG_VAL(0x18, 10, 9),
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
203 		.channel = BCM_SR_GENPLL4_CCN_CLK,
206 		.mdiv = REG_VAL(0x18, 0, 9),
209 		.channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
212 		.mdiv = REG_VAL(0x18, 10, 9),
215 		.channel = BCM_SR_GENPLL4_NOC_CLK,
218 		.mdiv = REG_VAL(0x18, 20, 9),
221 		.channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
223 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
224 		.mdiv = REG_VAL(0x1c, 0, 9),
227 		.channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
230 		.mdiv = REG_VAL(0x1c, 10, 9),
236 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll4_clk_init()
257 		.channel = BCM_SR_GENPLL5_FS4_HF_CLK,
259 		.mdiv = REG_VAL(0x18, 0, 9),
262 		.channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
264 		.mdiv = REG_VAL(0x18, 10, 9),
267 		.channel = BCM_SR_GENPLL5_RAID_AE_CLK,
269 		.mdiv = REG_VAL(0x18, 20, 9),
275 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_genpll5_clk_init()
293 		.channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
296 		.mdiv = REG_VAL(0x14, 0, 9),
299 		.channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
302 		.mdiv = REG_VAL(0x14, 10, 9),
305 		.channel = BCM_SR_LCPLL0_SATA_350_CLK,
307 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
308 		.mdiv = REG_VAL(0x14, 20, 9),
311 		.channel = BCM_SR_LCPLL0_SATA_500_CLK,
314 		.mdiv = REG_VAL(0x18, 0, 9),
320 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll0_clk_init()
338 		.channel = BCM_SR_LCPLL1_WAN_CLK,
341 		.mdiv = REG_VAL(0x14, 0, 9),
344 		.channel = BCM_SR_LCPLL1_USB_REF_CLK,
347 		.mdiv = REG_VAL(0x14, 10, 9),
350 		.channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
352 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
353 		.mdiv = REG_VAL(0x14, 20, 9),
359 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll1_clk_init()
377 		.channel = BCM_SR_LCPLL_PCIE_PHY_REF_CLK,
380 		.mdiv = REG_VAL(0x14, 0, 9),
386 	iproc_pll_clk_setup(pdev->dev.of_node,  in sr_lcpll_pcie_clk_init()
393 	{ .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
394 	{ .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
395 	{ .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
396 	{ .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
397 	{ .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
398 	{ .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
399 	{ .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
407 	probe_func = of_device_get_match_data(&pdev->dev);  in sr_clk_probe()
409 		return -ENODEV;  in sr_clk_probe()
416 		.name = "sr-clk",