Lines Matching +full:8 +full:- +full:channel

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
52 .mdiv = REG_VAL(0x18, 0, 8),
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
58 .mdiv = REG_VAL(0x18, 8, 8),
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
64 .mdiv = REG_VAL(0x14, 0, 8),
67 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
70 .mdiv = REG_VAL(0x14, 8, 8),
73 .channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
76 .mdiv = REG_VAL(0x14, 16, 8),
79 .channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
82 .mdiv = REG_VAL(0x14, 24, 8),
91 CLK_OF_DECLARE(ns2_genpll_src_clk, "brcm,ns2-genpll-scr",
111 .channel = BCM_NS2_GENPLL_SW_RPE_CLK,
114 .mdiv = REG_VAL(0x18, 0, 8),
117 .channel = BCM_NS2_GENPLL_SW_250_CLK,
120 .mdiv = REG_VAL(0x18, 8, 8),
123 .channel = BCM_NS2_GENPLL_SW_NIC_CLK,
126 .mdiv = REG_VAL(0x14, 0, 8),
129 .channel = BCM_NS2_GENPLL_SW_CHIMP_CLK,
132 .mdiv = REG_VAL(0x14, 8, 8),
135 .channel = BCM_NS2_GENPLL_SW_PORT_CLK,
138 .mdiv = REG_VAL(0x14, 16, 8),
141 .channel = BCM_NS2_GENPLL_SW_SDIO_CLK,
144 .mdiv = REG_VAL(0x14, 24, 8),
153 CLK_OF_DECLARE(ns2_genpll_sw_clk, "brcm,ns2-genpll-sw",
173 .channel = BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK,
176 .mdiv = REG_VAL(0x14, 0, 8),
179 .channel = BCM_NS2_LCPLL_DDR_DDR_CLK,
182 .mdiv = REG_VAL(0x14, 8, 8),
185 .channel = BCM_NS2_LCPLL_DDR_CH2_UNUSED,
188 .mdiv = REG_VAL(0x10, 0, 8),
191 .channel = BCM_NS2_LCPLL_DDR_CH3_UNUSED,
194 .mdiv = REG_VAL(0x10, 8, 8),
197 .channel = BCM_NS2_LCPLL_DDR_CH4_UNUSED,
200 .mdiv = REG_VAL(0x10, 16, 8),
203 .channel = BCM_NS2_LCPLL_DDR_CH5_UNUSED,
206 .mdiv = REG_VAL(0x10, 24, 8),
215 CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
235 .channel = BCM_NS2_LCPLL_PORTS_WAN_CLK,
238 .mdiv = REG_VAL(0x14, 0, 8),
241 .channel = BCM_NS2_LCPLL_PORTS_RGMII_CLK,
244 .mdiv = REG_VAL(0x14, 8, 8),
247 .channel = BCM_NS2_LCPLL_PORTS_CH2_UNUSED,
250 .mdiv = REG_VAL(0x10, 0, 8),
253 .channel = BCM_NS2_LCPLL_PORTS_CH3_UNUSED,
256 .mdiv = REG_VAL(0x10, 8, 8),
259 .channel = BCM_NS2_LCPLL_PORTS_CH4_UNUSED,
262 .mdiv = REG_VAL(0x10, 16, 8),
265 .channel = BCM_NS2_LCPLL_PORTS_CH5_UNUSED,
268 .mdiv = REG_VAL(0x10, 24, 8),
277 CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",