clk/bcm/clk-kona.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME		((const char *)-1)
33 #define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy)	((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy)		((policy)->offset != 0)
55 #define hyst_exists(hyst)		((hyst)->offset != 0)
60 						(div)->u.s.frac_width > 0)
62 #define selector_exists(sel)		((sel)->width != 0)
65 #define policy_lvm_en_exists(enable)	((enable)->offset != 0)
66 #define policy_ctl_exists(control)	((control)->offset != 0)
98  * Gating control and status is managed by a 32-bit gate register.
101  * - (no gate)
102  *     A clock with no gate is assumed to be always enabled.
103  * - hardware-only gating (auto-gating)
107  *     of auto-gated clocks can be read from the gate status bit.
108  * - software-only gating
109  *     Auto-gating is not available for this type of clock.
116  * - selectable hardware or software gating
131  *   HW         means this gate can be auto-gated
135  *   ENABLED    means this software-managed gate is *supposed* to be enabled
138 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
173 /* A hardware-or-enabled gate (enabled if not under hardware control) */
184 /* A software-only gate */
194 /* A hardware-only gate */
220  * output rate of the clock.  Each divider can be either fixed or
221  * variable.  If there are two dividers, they are the "pre-divider"
222  * and the "regular" or "downstream" divider.  If there is only one,
223  * there is no pre-divider.
225  * A fixed divider is any non-zero (positive) value, and it
226  * indicates how the input rate is affected by the divider.
228  * The value of a variable divider is maintained in a sub-field of a
229  * 32-bit divider register.  The position of the field in the
233  * In addition, a variable divider can indicate that some subset
234  * of its bits represent a "fractional" part of the divider.  Such
235  * bits comprise the low-order portion of the divider field, and can
236  * be viewed as representing the portion of the divider that lies to
238  * fractional bits.  Variable dividers with non-zero fraction width
240  * added 1 does *not* affect the low-order bit in this case, it
242  * code a divider field value is distinguished from the value it
245  * In order to avoid dealing with fractions, divider arithmetic is
247  * been left-shifted by the fractional width of a divider.  Dividing
252  * The recorded value of a variable divider can be modified.  To
253  * modify either divider (or both), a clock must be enabled (i.e.,
260 		struct {	/* variable divider */
261 			u32 offset;	/* divider register offset */
266 			u64 scaled_div;	/* scaled divider value */
268 		u32 fixed;	/* non-zero fixed divider value */
274  * Divider flags:
275  *   EXISTS means this divider exists
276  *   FIXED means it is a fixed-rate divider
278 #define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
279 #define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
281 /* Divider initialization macros */
283 /* A fixed (non-zero) divider */
290 /* A divider with an integral divisor */
291 #define DIVIDER(_offset, _shift, _width)				\  macro
300 /* A divider whose divisor has an integer and fractional part */
315  * sub-field of a 32-bit selector register.  The range of
322  * using a packed array (i.e., no empty slots) of (parent) clock
351  * Making changes to a variable divider or a selector for a clock
359  * case, the "pre-trigger" will be used when changing a clock's
360  * selector and/or its pre-divider.
394 #define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */