clk/bcm/clk-kona.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME		((const char *)-1)
33 #define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy)	((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy)		((policy)->offset != 0)
55 #define hyst_exists(hyst)		((hyst)->offset != 0)
60 						(div)->u.s.frac_width > 0)
62 #define selector_exists(sel)		((sel)->width != 0)
65 #define policy_lvm_en_exists(enable)	((enable)->offset != 0)
66 #define policy_ctl_exists(control)	((control)->offset != 0)  argument
77  * CCU policy control for clocks.  Clocks can be enabled or disabled
98  * Gating control and status is managed by a 32-bit gate register.
101  * - (no gate)
103  * - hardware-only gating (auto-gating)
107  *     of auto-gated clocks can be read from the gate status bit.
108  * - software-only gating
109  *     Auto-gating is not available for this type of clock.
112  *     under software control can be read from the gate status bit.
116  * - selectable hardware or software gating
118  *     under software or hardware control.  Which type is in use is
131  *   HW         means this gate can be auto-gated
133  *   NO_DISABLE means this gate is (only) enabled if under software control
134  *   SW_MANAGED means the status of this gate is under software control
135  *   ENABLED    means this software-managed gate is *supposed* to be enabled
138 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
139 #define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
141 #define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
147  * Any gate initially under software control will be enabled.
150 /* A hardware/software gate initially under software control */
162 /* A hardware/software gate initially under hardware control */
173 /* A hardware-or-enabled gate (enabled if not under hardware control) */
184 /* A software-only gate */
194 /* A hardware-only gate */
221  * variable.  If there are two dividers, they are the "pre-divider"
223  * there is no pre-divider.
225  * A fixed divider is any non-zero (positive) value, and it
228  * The value of a variable divider is maintained in a sub-field of a
229  * 32-bit divider register.  The position of the field in the
235  * bits comprise the low-order portion of the divider field, and can
238  * fractional bits.  Variable dividers with non-zero fraction width
240  * added 1 does *not* affect the low-order bit in this case, it
247  * been left-shifted by the fractional width of a divider.  Dividing
268 		u32 fixed;	/* non-zero fixed divider value */
276  *   FIXED means it is a fixed-rate divider
279 #define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
283 /* A fixed (non-zero) divider */
312  * Clocks may have multiple "parent" clocks.  If there is more than
313  * one, a selector must be specified to define which of the parent
315  * sub-field of a 32-bit selector register.  The range of
317  * available parent clocks.  Occasionally the reset value of a
321  * We register all known parent clocks with the common clock code
322  * using a packed array (i.e., no empty slots) of (parent) clock
337 	u32 *parent_sel;	/* array of parent selector values */
359  * case, the "pre-trigger" will be used when changing a clock's
360  * selector and/or its pre-divider.
394 #define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
423  * CCU policy control.  To enable software update of the policy
447 /* Policy control initialization macro */
458 	struct bcm_policy_ctl control;  member