Lines Matching refs:ctl_reg
491 u32 ctl_reg; member
514 u32 ctl_reg; member
933 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
1048 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy()
1065 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off()
1066 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off()
1080 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on()
1081 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on()
1119 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate()
1121 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate()
1269 cprman_write(cprman, data->ctl_reg, src); in bcm2835_clock_set_parent()
1278 u32 src = cprman_read(cprman, data->ctl_reg); in bcm2835_clock_get_parent()
1301 bcm2835_debugfs_regset(cprman, data->ctl_reg, in bcm2835_clock_debug_init()
1479 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1505 cprman->regs + gate_data->ctl_reg, in bcm2835_register_gate()
1944 .ctl_reg = CM_OTPCTL,
1956 .ctl_reg = CM_TIMERCTL,
1967 .ctl_reg = CM_TSENSCTL,
1974 .ctl_reg = CM_TECCTL,
1983 .ctl_reg = CM_H264CTL,
1991 .ctl_reg = CM_ISPCTL,
2004 .ctl_reg = CM_SDCCTL,
2012 .ctl_reg = CM_V3DCTL,
2026 .ctl_reg = CM_VPUCTL,
2038 .ctl_reg = CM_AVEOCTL,
2046 .ctl_reg = CM_CAM0CTL,
2054 .ctl_reg = CM_CAM1CTL,
2062 .ctl_reg = CM_DFTCTL,
2069 .ctl_reg = CM_DPICTL,
2079 .ctl_reg = CM_EMMCCTL,
2089 .ctl_reg = CM_EMMC2CTL,
2099 .ctl_reg = CM_GP0CTL,
2108 .ctl_reg = CM_GP1CTL,
2118 .ctl_reg = CM_GP2CTL,
2128 .ctl_reg = CM_HSMCTL,
2136 .ctl_reg = CM_PCMCTL,
2146 .ctl_reg = CM_PWMCTL,
2155 .ctl_reg = CM_SLIMCTL,
2164 .ctl_reg = CM_SMICTL,
2172 .ctl_reg = CM_UARTCTL,
2183 .ctl_reg = CM_VECCTL,
2198 .ctl_reg = CM_DSI0ECTL,
2206 .ctl_reg = CM_DSI1ECTL,
2214 .ctl_reg = CM_DSI0PCTL,
2222 .ctl_reg = CM_DSI1PCTL,
2240 .ctl_reg = CM_PERIICTL),