Lines Matching +full:clock +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0+
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
38 #include <dt-bindings/clock/bcm2835.h>
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
301 * with an external parent's name. This array is in the order that
321 * Real names of cprman clock parents looked up through
323 * parent_names[] arrays for clock registration.
337 writel(CM_PASSWORD | val, cprman->regs + reg); in cprman_write()
342 return readl(cprman->regs + reg); in cprman_read()
345 /* Does a cycle of measuring a clock through the TCNT clock, which may
355 spin_lock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
372 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); in bcm2835_measure_tcnt_mux()
383 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); in bcm2835_measure_tcnt_mux()
395 spin_unlock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
406 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); in bcm2835_debugfs_regset()
410 regset->regs = regs; in bcm2835_debugfs_regset()
411 regset->nregs = nregs; in bcm2835_debugfs_regset()
412 regset->base = cprman->regs + base; in bcm2835_debugfs_regset()
418 const char *name; member
434 * pre-divide-by-2.
470 const char *name; member
483 const char *name; member
511 const char *name; member
526 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_is_on()
527 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_is_on()
529 return cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_is_on()
537 * On BCM2711 there isn't a pre-divisor available in the PLL feedback in bcm2835_pll_get_prediv_mask()
538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed in bcm2835_pll_get_prediv_mask()
541 if (cprman->soc & SOC_BCM2711) in bcm2835_pll_get_prediv_mask()
544 return data->ana->fb_prediv_mask; in bcm2835_pll_get_prediv_mask()
557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); in bcm2835_pll_choose_ndiv_and_fdiv()
577 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_round_rate()
580 rate = clamp(rate, data->min_rate, data->max_rate); in bcm2835_pll_round_rate()
591 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_get_rate()
592 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_get_rate()
593 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_get_rate()
600 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; in bcm2835_pll_get_rate()
603 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & in bcm2835_pll_get_rate()
617 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_off()
618 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_off()
620 spin_lock(&cprman->regs_lock); in bcm2835_pll_off()
621 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); in bcm2835_pll_off()
622 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_off()
623 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_off()
625 spin_unlock(&cprman->regs_lock); in bcm2835_pll_off()
631 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_on()
632 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_on()
635 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
636 cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_on()
640 spin_lock(&cprman->regs_lock); in bcm2835_pll_on()
641 cprman_write(cprman, data->cm_ctrl_reg, in bcm2835_pll_on()
642 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); in bcm2835_pll_on()
643 spin_unlock(&cprman->regs_lock); in bcm2835_pll_on()
647 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { in bcm2835_pll_on()
649 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_pll_on()
651 return -ETIMEDOUT; in bcm2835_pll_on()
657 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
658 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_on()
671 * ANA3-ANA0, in that order. This lets us write all 4 in bcm2835_pll_write_ana()
674 * 3 individually through their partial-write registers, each in bcm2835_pll_write_ana()
677 for (i = 3; i >= 0; i--) in bcm2835_pll_write_ana()
685 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_set_rate()
686 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_set_rate()
693 if (rate > data->max_fb_rate) { in bcm2835_pll_set_rate()
702 for (i = 3; i >= 0; i--) in bcm2835_pll_set_rate()
703 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); in bcm2835_pll_set_rate()
707 ana[0] &= ~data->ana->mask0; in bcm2835_pll_set_rate()
708 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
709 ana[1] &= ~data->ana->mask1; in bcm2835_pll_set_rate()
710 ana[1] |= data->ana->set1; in bcm2835_pll_set_rate()
711 ana[3] &= ~data->ana->mask3; in bcm2835_pll_set_rate()
712 ana[3] |= data->ana->set3; in bcm2835_pll_set_rate()
724 /* Unmask the reference clock from the oscillator. */ in bcm2835_pll_set_rate()
725 spin_lock(&cprman->regs_lock); in bcm2835_pll_set_rate()
728 data->reference_enable_mask); in bcm2835_pll_set_rate()
729 spin_unlock(&cprman->regs_lock); in bcm2835_pll_set_rate()
732 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
735 cprman_write(cprman, data->frac_reg, fdiv); in bcm2835_pll_set_rate()
737 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_set_rate()
742 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); in bcm2835_pll_set_rate()
745 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
754 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_debug_init()
755 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_debug_init()
758 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_debug_init()
762 regs[0].name = "cm_ctrl"; in bcm2835_pll_debug_init()
763 regs[0].offset = data->cm_ctrl_reg; in bcm2835_pll_debug_init()
764 regs[1].name = "a2w_ctrl"; in bcm2835_pll_debug_init()
765 regs[1].offset = data->a2w_ctrl_reg; in bcm2835_pll_debug_init()
766 regs[2].name = "frac"; in bcm2835_pll_debug_init()
767 regs[2].offset = data->frac_reg; in bcm2835_pll_debug_init()
768 regs[3].name = "ana0"; in bcm2835_pll_debug_init()
769 regs[3].offset = data->ana_reg_base + 0 * 4; in bcm2835_pll_debug_init()
770 regs[4].name = "ana1"; in bcm2835_pll_debug_init()
771 regs[4].offset = data->ana_reg_base + 1 * 4; in bcm2835_pll_debug_init()
772 regs[5].name = "ana2"; in bcm2835_pll_debug_init()
773 regs[5].offset = data->ana_reg_base + 2 * 4; in bcm2835_pll_debug_init()
774 regs[6].name = "ana3"; in bcm2835_pll_debug_init()
775 regs[6].offset = data->ana_reg_base + 3 * 4; in bcm2835_pll_debug_init()
805 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_is_on()
806 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_is_on()
808 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); in bcm2835_pll_divider_is_on()
826 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_off()
827 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_off()
829 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_off()
830 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_off()
831 (cprman_read(cprman, data->cm_reg) & in bcm2835_pll_divider_off()
832 ~data->load_mask) | data->hold_mask); in bcm2835_pll_divider_off()
833 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_off()
834 cprman_read(cprman, data->a2w_reg) | in bcm2835_pll_divider_off()
836 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_off()
842 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_on()
843 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_on()
845 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_on()
846 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_on()
847 cprman_read(cprman, data->a2w_reg) & in bcm2835_pll_divider_on()
850 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_on()
851 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); in bcm2835_pll_divider_on()
852 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_on()
862 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_set_rate()
863 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_set_rate()
872 cprman_write(cprman, data->a2w_reg, div); in bcm2835_pll_divider_set_rate()
873 cm = cprman_read(cprman, data->cm_reg); in bcm2835_pll_divider_set_rate()
874 cprman_write(cprman, data->cm_reg, cm | data->load_mask); in bcm2835_pll_divider_set_rate()
875 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); in bcm2835_pll_divider_set_rate()
884 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_debug_init()
885 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_debug_init()
888 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_divider_debug_init()
892 regs[0].name = "cm"; in bcm2835_pll_divider_debug_init()
893 regs[0].offset = data->cm_reg; in bcm2835_pll_divider_debug_init()
894 regs[1].name = "a2w"; in bcm2835_pll_divider_debug_init()
895 regs[1].offset = data->a2w_reg; in bcm2835_pll_divider_debug_init()
911 * The CM dividers do fixed-point division, so we can't use the
913 * fake it by having some fixed shifts preceding it in the clock tree,
914 * because we'd run out of bits in a 32-bit unsigned long).
929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_is_on() local
930 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_is_on()
931 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_is_on()
933 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
940 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_choose_div() local
941 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div()
943 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; in bcm2835_clock_choose_div()
951 /* different clamping limits apply for a mash clock */ in bcm2835_clock_choose_div()
952 if (data->is_mash_clock) { in bcm2835_clock_choose_div()
956 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; in bcm2835_clock_choose_div()
961 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, in bcm2835_clock_choose_div()
962 CM_DIV_FRAC_BITS - data->frac_bits); in bcm2835_clock_choose_div()
972 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, in bcm2835_clock_rate_from_divisor() argument
976 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_rate_from_divisor()
979 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_rate_from_divisor()
984 * the bits are populated in any given clock. in bcm2835_clock_rate_from_divisor()
986 div >>= CM_DIV_FRAC_BITS - data->frac_bits; in bcm2835_clock_rate_from_divisor()
987 div &= (1 << (data->int_bits + data->frac_bits)) - 1; in bcm2835_clock_rate_from_divisor()
992 temp = (u64)parent_rate << data->frac_bits; in bcm2835_clock_rate_from_divisor()
1011 * If increasing a clock by less than 0.1% changes it in bcm2835_round_rate()
1014 if ((rate + scaler - 1) / scaler % 1000 == 0) in bcm2835_round_rate()
1023 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_get_rate() local
1024 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_rate()
1025 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_rate()
1029 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_get_rate()
1032 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1034 rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div); in bcm2835_clock_get_rate()
1036 if (data->round_up) in bcm2835_clock_get_rate()
1042 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) in bcm2835_clock_wait_busy() argument
1044 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_wait_busy()
1045 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_wait_busy()
1048 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy()
1050 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_clock_wait_busy()
1051 clk_hw_get_name(&clock->hw)); in bcm2835_clock_wait_busy()
1060 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_off() local
1061 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_off()
1062 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_off()
1064 spin_lock(&cprman->regs_lock); in bcm2835_clock_off()
1065 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off()
1066 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off()
1067 spin_unlock(&cprman->regs_lock); in bcm2835_clock_off()
1070 bcm2835_clock_wait_busy(clock); in bcm2835_clock_off()
1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_on() local
1076 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_on()
1077 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_on()
1079 spin_lock(&cprman->regs_lock); in bcm2835_clock_on()
1080 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on()
1081 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on()
1084 spin_unlock(&cprman->regs_lock); in bcm2835_clock_on()
1086 /* Debug code to measure the clock once it's turned on to see in bcm2835_clock_on()
1089 if (data->tcnt_mux && false) { in bcm2835_clock_on()
1090 dev_info(cprman->dev, in bcm2835_clock_on()
1092 data->name, in bcm2835_clock_on()
1094 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); in bcm2835_clock_on()
1103 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_set_rate() local
1104 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_rate()
1105 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_rate()
1109 spin_lock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1114 * In principle it is recommended to stop/start the clock first, in bcm2835_clock_set_rate()
1116 * clock this requirement should be take care of by the in bcm2835_clock_set_rate()
1117 * clk-framework. in bcm2835_clock_set_rate()
1119 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate()
1121 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate()
1123 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1125 spin_unlock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1146 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_choose_div_and_prate() local
1147 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_choose_div_and_prate()
1148 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div_and_prate()
1155 if (!(BIT(parent_idx) & data->set_rate_parent)) { in bcm2835_clock_choose_div_and_prate()
1159 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div); in bcm2835_clock_choose_div_and_prate()
1161 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { in bcm2835_clock_choose_div_and_prate()
1165 high = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1168 low = bcm2835_clock_rate_from_divisor(clock, *prate, in bcm2835_clock_choose_div_and_prate()
1175 return *avgrate - max(*avgrate - low, high - *avgrate); in bcm2835_clock_choose_div_and_prate()
1180 if (data->frac_bits) in bcm2835_clock_choose_div_and_prate()
1181 dev_warn(cprman->dev, in bcm2835_clock_choose_div_and_prate()
1184 /* clamp to min divider of 2 if we're dealing with a mash clock */ in bcm2835_clock_choose_div_and_prate()
1185 mindiv = data->is_mash_clock ? 2 : 1; in bcm2835_clock_choose_div_and_prate()
1186 maxdiv = BIT(data->int_bits) - 1; in bcm2835_clock_choose_div_and_prate()
1223 * Select parent clock that results in the closest but lower rate in bcm2835_clock_determine_rate()
1231 * Don't choose a PLLC-derived clock as our parent in bcm2835_clock_determine_rate()
1234 * over-temp or under-voltage conditions, without in bcm2835_clock_determine_rate()
1235 * prior notification to our clock consumer. in bcm2835_clock_determine_rate()
1240 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, in bcm2835_clock_determine_rate()
1243 if (abs(req->rate - rate) < abs(req->rate - best_rate)) { in bcm2835_clock_determine_rate()
1252 return -EINVAL; in bcm2835_clock_determine_rate()
1254 req->best_parent_hw = best_parent; in bcm2835_clock_determine_rate()
1255 req->best_parent_rate = best_prate; in bcm2835_clock_determine_rate()
1257 req->rate = best_avgrate; in bcm2835_clock_determine_rate()
1264 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_set_parent() local
1265 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_parent()
1266 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_parent()
1269 cprman_write(cprman, data->ctl_reg, src); in bcm2835_clock_set_parent()
1275 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_get_parent() local
1276 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_parent()
1277 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_parent()
1278 u32 src = cprman_read(cprman, data->ctl_reg); in bcm2835_clock_get_parent()
1285 .name = "ctl",
1289 .name = "div",
1297 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); in bcm2835_clock_debug_init() local
1298 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_debug_init()
1299 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_debug_init()
1301 bcm2835_debugfs_regset(cprman, data->ctl_reg, in bcm2835_clock_debug_init()
1325 * The VPU clock can never be disabled (it doesn't have an ENABLE
1326 * bit), so it gets its own set of clock ops.
1349 init.parent_names = &cprman->real_parent_names[0]; in bcm2835_register_pll()
1351 init.name = pll_data->name; in bcm2835_register_pll()
1353 init.flags = pll_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll()
1359 pll->cprman = cprman; in bcm2835_register_pll()
1360 pll->data = pll_data; in bcm2835_register_pll()
1361 pll->hw.init = &init; in bcm2835_register_pll()
1363 ret = devm_clk_hw_register(cprman->dev, &pll->hw); in bcm2835_register_pll()
1368 return &pll->hw; in bcm2835_register_pll()
1381 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1382 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, in bcm2835_register_pll_divider()
1383 "%s_prediv", divider_data->name); in bcm2835_register_pll_divider()
1387 divider_name = divider_data->name; in bcm2835_register_pll_divider()
1392 init.parent_names = ÷r_data->source_pll; in bcm2835_register_pll_divider()
1394 init.name = divider_name; in bcm2835_register_pll_divider()
1396 init.flags = divider_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll_divider()
1398 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); in bcm2835_register_pll_divider()
1402 divider->div.reg = cprman->regs + divider_data->a2w_reg; in bcm2835_register_pll_divider()
1403 divider->div.shift = A2W_PLL_DIV_SHIFT; in bcm2835_register_pll_divider()
1404 divider->div.width = A2W_PLL_DIV_BITS; in bcm2835_register_pll_divider()
1405 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; in bcm2835_register_pll_divider()
1406 divider->div.lock = &cprman->regs_lock; in bcm2835_register_pll_divider()
1407 divider->div.hw.init = &init; in bcm2835_register_pll_divider()
1408 divider->div.table = NULL; in bcm2835_register_pll_divider()
1410 divider->cprman = cprman; in bcm2835_register_pll_divider()
1411 divider->data = divider_data; in bcm2835_register_pll_divider()
1413 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); in bcm2835_register_pll_divider()
1421 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1422 return clk_hw_register_fixed_factor(cprman->dev, in bcm2835_register_pll_divider()
1423 divider_data->name, in bcm2835_register_pll_divider()
1427 divider_data->fixed_divider); in bcm2835_register_pll_divider()
1430 return ÷r->div.hw; in bcm2835_register_pll_divider()
1437 struct bcm2835_clock *clock; in bcm2835_register_clock() local
1445 * actual clock-output-name of the parent. in bcm2835_register_clock()
1447 for (i = 0; i < clock_data->num_mux_parents; i++) { in bcm2835_register_clock()
1448 parents[i] = clock_data->parents[i]; in bcm2835_register_clock()
1454 parents[i] = cprman->real_parent_names[ret]; in bcm2835_register_clock()
1459 init.num_parents = clock_data->num_mux_parents; in bcm2835_register_clock()
1460 init.name = clock_data->name; in bcm2835_register_clock()
1461 init.flags = clock_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_clock()
1467 if (clock_data->set_rate_parent) in bcm2835_register_clock()
1470 if (clock_data->is_vpu_clock) { in bcm2835_register_clock()
1476 /* If the clock wasn't actually enabled at boot, it's not in bcm2835_register_clock()
1479 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1483 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); in bcm2835_register_clock()
1484 if (!clock) in bcm2835_register_clock()
1487 clock->cprman = cprman; in bcm2835_register_clock()
1488 clock->data = clock_data; in bcm2835_register_clock()
1489 clock->hw.init = &init; in bcm2835_register_clock()
1491 ret = devm_clk_hw_register(cprman->dev, &clock->hw); in bcm2835_register_clock()
1494 return &clock->hw; in bcm2835_register_clock()
1502 return clk_hw_register_gate(cprman->dev, gate_data->name, in bcm2835_register_gate()
1503 gate_data->parent, in bcm2835_register_gate()
1505 cprman->regs + gate_data->ctl_reg, in bcm2835_register_gate()
1506 CM_GATE_BIT, 0, &cprman->regs_lock); in bcm2835_register_gate()
1516 /* assignment helper macros for different clock types */
1572 * Restrict clock sources for the PCM peripheral to the oscillator and
1581 "-",
1583 "-",
1584 "-",
1585 "-",
1586 "-",
1588 "-",
1669 * (Compact Camera Port 2) transmitter clock.
1676 .name = "plla",
1691 .name = "plla_core",
1701 .name = "plla_per",
1711 .name = "plla_dsi0",
1720 .name = "plla_ccp2",
1729 /* PLLB is used for the ARM's clock. */
1732 .name = "pllb",
1748 .name = "pllb_arm",
1758 * PLLC is the core PLL, used to drive the core VPU clock.
1765 .name = "pllc",
1780 .name = "pllc_core0",
1790 .name = "pllc_core1",
1800 .name = "pllc_core2",
1810 .name = "pllc_per",
1827 .name = "plld",
1842 .name = "plld_core",
1857 .name = "plld_per",
1867 .name = "plld_dsi0",
1876 .name = "plld_dsi1",
1885 * PLLH is used to supply the pixel clock or the AUX clock for the
1907 .name = "pllh_rcal",
1917 .name = "pllh_aux",
1927 .name = "pllh_pix",
1940 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1943 .name = "otp",
1950 * Used for a 1Mhz clock for the system clocksource, and also used
1955 .name = "timer",
1961 * Clock for the temperature sensor.
1966 .name = "tsens",
1973 .name = "tec",
1982 .name = "h264",
1990 .name = "isp",
1998 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
2003 .name = "sdram",
2011 .name = "v3d",
2018 * VPU clock. This doesn't have an enable bit, since it drives
2025 .name = "vpu",
2037 .name = "aveo",
2045 .name = "cam0",
2053 .name = "cam1",
2061 .name = "dft",
2068 .name = "dpi",
2075 /* Arasan EMMC clock */
2078 .name = "emmc",
2085 /* EMMC2 clock (only available for BCM2711) */
2088 .name = "emmc2",
2098 .name = "gp0",
2107 .name = "gp1",
2117 .name = "gp2",
2127 .name = "hsm",
2135 .name = "pcm",
2145 .name = "pwm",
2154 .name = "slim",
2163 .name = "smi",
2171 .name = "uart",
2179 /* TV encoder clock. Only operating frequency is 108Mhz. */
2182 .name = "vec",
2197 .name = "dsi0e",
2205 .name = "dsi1e",
2213 .name = "dsi0p",
2221 .name = "dsi1p",
2234 * non-stop vpu clock.
2238 .name = "peri_image",
2244 * Permanently take a reference on the parent of the SDRAM clock.
2248 * periodically switches the SDRAM to using our CM clock to do PVT
2264 struct device *dev = &pdev->dev; in bcm2835_clk_probe()
2273 pdata = of_device_get_match_data(&pdev->dev); in bcm2835_clk_probe()
2275 return -ENODEV; in bcm2835_clk_probe()
2281 return -ENOMEM; in bcm2835_clk_probe()
2283 spin_lock_init(&cprman->regs_lock); in bcm2835_clk_probe()
2284 cprman->dev = dev; in bcm2835_clk_probe()
2285 cprman->regs = devm_platform_ioremap_resource(pdev, 0); in bcm2835_clk_probe()
2286 if (IS_ERR(cprman->regs)) in bcm2835_clk_probe()
2287 return PTR_ERR(cprman->regs); in bcm2835_clk_probe()
2289 memcpy(cprman->real_parent_names, cprman_parent_names, in bcm2835_clk_probe()
2291 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, in bcm2835_clk_probe()
2301 if (!cprman->real_parent_names[0]) in bcm2835_clk_probe()
2302 return -ENODEV; in bcm2835_clk_probe()
2306 cprman->onecell.num = asize; in bcm2835_clk_probe()
2307 cprman->soc = pdata->soc; in bcm2835_clk_probe()
2308 hws = cprman->onecell.hws; in bcm2835_clk_probe()
2312 if (desc->clk_register && desc->data && in bcm2835_clk_probe()
2313 (desc->supported & pdata->soc)) { in bcm2835_clk_probe()
2314 hws[i] = desc->clk_register(cprman, desc->data); in bcm2835_clk_probe()
2318 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); in bcm2835_clk_probe()
2322 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, in bcm2835_clk_probe()
2323 &cprman->onecell); in bcm2835_clk_probe()
2335 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2336 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2343 .name = "bcm2835-clk",
2352 MODULE_DESCRIPTION("BCM2835 clock driver");