Lines Matching full:eth_clk
142 CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
145 CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
148 CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
163 CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
185 "eth_clk", CCU_SYS_GMAC0_BASE, 5),
187 "eth_clk", 10),
189 "eth_clk", CCU_SYS_GMAC1_BASE, 5),
191 "eth_clk", 10),
193 "eth_clk", CCU_SYS_XGMAC_BASE, 1),
199 "eth_clk", CCU_SYS_USB_BASE, 10),
207 "eth_clk", CCU_SYS_UART_BASE, 17,
210 "eth_clk", 10),
212 "eth_clk", 10),
225 "eth_clk", CCU_SYS_WDT_BASE, 17,