77 					      unsigned long od)  in ccu_pll_calc_freq()  argument
83 	do_div(tmp, od);  in ccu_pll_calc_freq()
156 	unsigned long nr, nf, od;  in ccu_pll_recalc_rate()  local
162 	od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;  in ccu_pll_recalc_rate()
164 	return ccu_pll_calc_freq(parent_rate, nr, nf, od);  in ccu_pll_recalc_rate()
169 				 unsigned long *od)  in ccu_pll_calc_factors()  argument
184 	 * Find a closest [nr;nf;od] vector taking into account the  in ccu_pll_calc_factors()
185 	 * limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is  in ccu_pll_calc_factors()
190 		/* Use Od factor to fulfill the limitation 2). */  in ccu_pll_calc_factors()
226 			*od = CCU_PLL_CLKOD_FACTOR * d1;  in ccu_pll_calc_factors()
234 	unsigned long nr = 1, nf = 1, od = 1;  in ccu_pll_round_rate()  local
236 	ccu_pll_calc_factors(rate, *parent_rate, &nr, &nf, &od);  in ccu_pll_round_rate()
238 	return ccu_pll_calc_freq(*parent_rate, nr, nf, od);  in ccu_pll_round_rate()
249 	unsigned long nr, nf, od;  in ccu_pll_set_rate_reset()  local
254 	ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);  in ccu_pll_set_rate_reset()
260 	      FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);  in ccu_pll_set_rate_reset()
280 	unsigned long nr, nf, od;  in ccu_pll_set_rate_norst()  local
284 	ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);  in ccu_pll_set_rate_norst()
294 	      FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);  in ccu_pll_set_rate_norst()