1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
28  * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
33  * reg should be an u32 variable.
36 #define PLL_REG_GET_LOW(reg)			\  argument
37 	(((reg) & (0x3F << 0)) >> 0)
38 #define PLL_REG_GET_HIGH(reg)			\  argument
39 	(((reg) & (0x3F << 6)) >> 6)
40 #define PLL_REG_GET_EDGE(reg)			\  argument
41 	(((reg) & (BIT(12))) ? 1 : 0)
42 #define PLL_REG_GET_BYPASS(reg)			\  argument
43 	(((reg) & (BIT(13))) ? 1 : 0)
44 #define PLL_REG_GET_NOUPD(reg)			\  argument
45 	(((reg) & (BIT(14))) ? 1 : 0)
46 #define PLL_REG_GET_PAD(reg)			\  argument
47 	(((reg) & (0x1FFFF << 15)) >> 15)
49 #define PLL_REG_SET_LOW(reg, value)		\  argument
50 	{ reg |= (((value) & 0x3F) << 0); }
51 #define PLL_REG_SET_HIGH(reg, value)		\  argument
52 	{ reg |= (((value) & 0x3F) << 6); }
53 #define PLL_REG_SET_EDGE(reg, value)		\  argument
54 	{ reg |= (((value) & 0x01) << 12); }
55 #define PLL_REG_SET_BYPASS(reg, value)		\  argument
56 	{ reg |= (((value) & 0x01) << 13); }
57 #define PLL_REG_SET_NOUPD(reg, value)		\  argument
58 	{ reg |= (((value) & 0x01) << 14); }
59 #define PLL_REG_SET_PAD(reg, value)		\  argument
60 	{ reg |= (((value) & 0x1FFFF) << 15); }
98 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,  in axs10x_pll_write()  argument
101 	iowrite32(val, clk->base + reg);  in axs10x_pll_write()
104 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)  in axs10x_pll_read()  argument
106 	return ioread32(clk->base + reg);  in axs10x_pll_read()
114 static inline u32 axs10x_div_get_value(u32 reg)  in axs10x_div_get_value()  argument
116 	if (PLL_REG_GET_BYPASS(reg))  in axs10x_div_get_value()
119 	return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);  in axs10x_div_get_value()
158 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;  in axs10x_pll_round_rate()
161 		return -EINVAL;  in axs10x_pll_round_rate()
166 		if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))  in axs10x_pll_round_rate()
178 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;  in axs10x_pll_set_rate()
194 			if (!(ioread32(clk->lock) & PLL_LOCK))  in axs10x_pll_set_rate()
195 				return -ETIMEDOUT;  in axs10x_pll_set_rate()
197 			if (ioread32(clk->lock) & PLL_ERROR)  in axs10x_pll_set_rate()
198 				return -EINVAL;  in axs10x_pll_set_rate()
204 	dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,  in axs10x_pll_set_rate()
206 	return -EINVAL;  in axs10x_pll_set_rate()
217 	struct device *dev = &pdev->dev;  in axs10x_pll_clk_probe()
220 	struct clk_init_data init = { };  in axs10x_pll_clk_probe()  local
225 		return -ENOMEM;  in axs10x_pll_clk_probe()
227 	pll_clk->base = devm_platform_ioremap_resource(pdev, 0);  in axs10x_pll_clk_probe()
228 	if (IS_ERR(pll_clk->base))  in axs10x_pll_clk_probe()
229 		return PTR_ERR(pll_clk->base);  in axs10x_pll_clk_probe()
231 	pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);  in axs10x_pll_clk_probe()
232 	if (IS_ERR(pll_clk->lock))  in axs10x_pll_clk_probe()
233 		return PTR_ERR(pll_clk->lock);  in axs10x_pll_clk_probe()
235 	init.name = dev->of_node->name;  in axs10x_pll_clk_probe()
236 	init.ops = &axs10x_pll_ops;  in axs10x_pll_clk_probe()
237 	parent_name = of_clk_get_parent_name(dev->of_node, 0);  in axs10x_pll_clk_probe()
238 	init.parent_names = &parent_name;  in axs10x_pll_clk_probe()
239 	init.num_parents = 1;  in axs10x_pll_clk_probe()
240 	pll_clk->hw.init = &init;  in axs10x_pll_clk_probe()
241 	pll_clk->dev = dev;  in axs10x_pll_clk_probe()
242 	pll_clk->pll_cfg = of_device_get_match_data(dev);  in axs10x_pll_clk_probe()
244 	if (!pll_clk->pll_cfg) {  in axs10x_pll_clk_probe()
246 		return -EINVAL;  in axs10x_pll_clk_probe()
249 	ret = devm_clk_hw_register(dev, &pll_clk->hw);  in axs10x_pll_clk_probe()
251 		dev_err(dev, "failed to register %s clock\n", init.name);  in axs10x_pll_clk_probe()
256 					   &pll_clk->hw);  in axs10x_pll_clk_probe()
263 	struct clk_init_data init = { };  in of_axs10x_pll_clk_setup()  local
270 	pll_clk->base = of_iomap(node, 0);  in of_axs10x_pll_clk_setup()
271 	if (!pll_clk->base) {  in of_axs10x_pll_clk_setup()
276 	pll_clk->lock = of_iomap(node, 1);  in of_axs10x_pll_clk_setup()
277 	if (!pll_clk->lock) {  in of_axs10x_pll_clk_setup()
282 	init.name = node->name;  in of_axs10x_pll_clk_setup()
283 	init.ops = &axs10x_pll_ops;  in of_axs10x_pll_clk_setup()
285 	init.parent_names = &parent_name;  in of_axs10x_pll_clk_setup()
286 	init.num_parents = parent_name ? 1 : 0;  in of_axs10x_pll_clk_setup()
287 	pll_clk->hw.init = &init;  in of_axs10x_pll_clk_setup()
288 	pll_clk->pll_cfg = arc_pll_cfg;  in of_axs10x_pll_clk_setup()
290 	ret = clk_hw_register(NULL, &pll_clk->hw);  in of_axs10x_pll_clk_setup()
296 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);  in of_axs10x_pll_clk_setup()
305 	clk_hw_unregister(&pll_clk->hw);  in of_axs10x_pll_clk_setup()
307 	iounmap(pll_clk->lock);  in of_axs10x_pll_clk_setup()
309 	iounmap(pll_clk->base);  in of_axs10x_pll_clk_setup()
313 CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
317 	{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
324 		.name = "axs10x-pll-clock",