38 static int clk_generated_set(struct clk_generated *gck, int status)  in clk_generated_set()  argument
43 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_set()
44 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_set()
45 		     (gck->id & gck->layout->pid_mask));  in clk_generated_set()
46 	regmap_update_bits(gck->regmap, gck->layout->offset,  in clk_generated_set()
47 			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |  in clk_generated_set()
48 			   gck->layout->cmd | enable,  in clk_generated_set()
49 			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |  in clk_generated_set()
50 			   gck->layout->cmd |  in clk_generated_set()
51 			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |  in clk_generated_set()
53 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_set()
60 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_enable()  local
63 		 __func__, gck->gckdiv, gck->parent_id);  in clk_generated_enable()
65 	clk_generated_set(gck, 1);  in clk_generated_enable()
72 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_disable()  local
75 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_disable()
76 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_disable()
77 		     (gck->id & gck->layout->pid_mask));  in clk_generated_disable()
78 	regmap_update_bits(gck->regmap, gck->layout->offset,  in clk_generated_disable()
79 			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,  in clk_generated_disable()
80 			   gck->layout->cmd);  in clk_generated_disable()
81 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_disable()
86 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_is_enabled()  local
90 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_is_enabled()
91 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_is_enabled()
92 		     (gck->id & gck->layout->pid_mask));  in clk_generated_is_enabled()
93 	regmap_read(gck->regmap, gck->layout->offset, &status);  in clk_generated_is_enabled()
94 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_is_enabled()
103 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_recalc_rate()  local
105 	return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);  in clk_generated_recalc_rate()
137 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_determine_rate()  local
146 	if (gck->range.max && req->rate > gck->range.max)  in clk_generated_determine_rate()
147 		req->rate = gck->range.max;  in clk_generated_determine_rate()
148 	if (gck->range.min && req->rate < gck->range.min)  in clk_generated_determine_rate()
149 		req->rate = gck->range.min;  in clk_generated_determine_rate()
152 		if (gck->chg_pid == i)  in clk_generated_determine_rate()
162 		    (gck->range.max && min_rate > gck->range.max))  in clk_generated_determine_rate()
183 	 * that the only clks able to modify gck rate are those of audio IPs.  in clk_generated_determine_rate()
186 	if (gck->chg_pid < 0)  in clk_generated_determine_rate()
189 	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);  in clk_generated_determine_rate()
212 	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))  in clk_generated_determine_rate()
222 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_set_parent()  local
227 	if (gck->mux_table)  in clk_generated_set_parent()
228 		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);  in clk_generated_set_parent()
230 		gck->parent_id = index;  in clk_generated_set_parent()
237 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_get_parent()  local
239 	return gck->parent_id;  in clk_generated_get_parent()
247 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_set_rate()  local
253 	if (gck->range.max && rate > gck->range.max)  in clk_generated_set_rate()
260 	gck->gckdiv = div - 1;  in clk_generated_set_rate()
266 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_save_context()  local
268 	gck->pms.status = clk_generated_is_enabled(&gck->hw);  in clk_generated_save_context()
275 	struct clk_generated *gck = to_clk_generated(hw);  in clk_generated_restore_context()  local
277 	if (gck->pms.status)  in clk_generated_restore_context()
278 		clk_generated_set(gck, gck->pms.status);  in clk_generated_restore_context()
298  * @gck:	Generated clock to set the startup parameters for.
303 static void clk_generated_startup(struct clk_generated *gck)  in clk_generated_startup()  argument
308 	spin_lock_irqsave(gck->lock, flags);  in clk_generated_startup()
309 	regmap_write(gck->regmap, gck->layout->offset,  in clk_generated_startup()
310 		     (gck->id & gck->layout->pid_mask));  in clk_generated_startup()
311 	regmap_read(gck->regmap, gck->layout->offset, &tmp);  in clk_generated_startup()
312 	spin_unlock_irqrestore(gck->lock, flags);  in clk_generated_startup()
314 	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);  in clk_generated_startup()
315 	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);  in clk_generated_startup()
327 	struct clk_generated *gck;  in at91_clk_register_generated()  local
335 	gck = kzalloc(sizeof(*gck), GFP_KERNEL);  in at91_clk_register_generated()
336 	if (!gck)  in at91_clk_register_generated()
350 	gck->id = id;  in at91_clk_register_generated()
351 	gck->hw.init = &init;  in at91_clk_register_generated()
352 	gck->regmap = regmap;  in at91_clk_register_generated()
353 	gck->lock = lock;  in at91_clk_register_generated()
354 	gck->range = *range;  in at91_clk_register_generated()
355 	gck->chg_pid = chg_pid;  in at91_clk_register_generated()
356 	gck->layout = layout;  in at91_clk_register_generated()
357 	gck->mux_table = mux_table;  in at91_clk_register_generated()
359 	clk_generated_startup(gck);  in at91_clk_register_generated()
360 	hw = &gck->hw;  in at91_clk_register_generated()
361 	ret = clk_hw_register(NULL, &gck->hw);  in at91_clk_register_generated()
363 		kfree(gck);  in at91_clk_register_generated()