Lines Matching refs:TLCLK_REG0
137 #define TLCLK_REG0 TLCLK_BASE macro
517 SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); in store_select_amcb2_transmit_clock()
520 SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); in store_select_amcb2_transmit_clock()
523 SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); in store_select_amcb2_transmit_clock()
526 SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); in store_select_amcb2_transmit_clock()
559 SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); in store_select_amcb1_transmit_clock()
562 SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); in store_select_amcb1_transmit_clock()
565 SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); in store_select_amcb1_transmit_clock()
568 SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); in store_select_amcb1_transmit_clock()
636 SET_PORT_BITS(TLCLK_REG0, 0xfb, val); in store_filter_select()
656 SET_PORT_BITS(TLCLK_REG0, 0xbf, val); in store_hardware_switching_mode()
677 SET_PORT_BITS(TLCLK_REG0, 0x7f, val); in store_hardware_switching()
695 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); in store_refalign()
696 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08); in store_refalign()
697 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); in store_refalign()
717 SET_PORT_BITS(TLCLK_REG0, 0xcf, val); in store_mode_select()