Lines Matching +full:queue +full:- +full:rx

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
36 /* Registers for MSI-X */
60 /* Minimum and Maximum number of MSI-X Vector
72 /* The number of descriptors in TX/RX queues */
75 /* Number of Queue for TX and RX
84 /* The size of DMA buffer for TX and RX in bytes */
95 /* Number of pending RX requests for downlink */
107 * All members are write-only for host and read-only for device.
120 * @addr_tfdq: Address of TFD Queue(tx)
121 * @addr_urbdq0: Address of URBD Queue(tx)
122 * @num_tfdq: Number of TFD in TFD Queue(tx)
123 * @num_urbdq0: Number of URBD in URBD Queue(tx)
124 * @tfdq_db_vec: Queue number of TFD
125 * @urbdq0_db_vec: Queue number of URBD
126 * @addr_frbdq: Address of FRBD Queue(rx)
127 * @addr_urbdq1: Address of URBD Queue(rx)
128 * @num_frbdq: Number of FRBD in FRBD Queue(rx)
129 * @frbdq_db_vec: Queue number of FRBD
130 * @num_urbdq1: Number of URBD in URBD Queue(rx)
131 * @urbdq_db_vec: Queue number of URBDQ1
132 * @tr_msi_vec: Transfer Ring MSI-X Vector
133 * @cr_msi_vec: Completion Ring MSI-X Vector
206 * @num_txq: Queue index of TFD Queue
218 /* FRB Descriptor for RX
219 * @tag: RX buffer tag (index of RX buffer queue)
229 /* URB Descriptor for RX
240 /* RFH header in RX packet
242 * @rxq: RX Queue number
274 /* Structure for TX Queue
294 /* Structure for RX Queue
318 * @irq_lock: spinlock for MSI-X
319 * @hci_rx_lock: spinlock for HCI RX flow
321 * @msix_entries: array of MSI-X entries
322 * @msix_enabled: true if MSI-X is enabled;
335 * @workqueue: workqueue for RX work
336 * @rx_skb_q: SKB queue for RX packet
337 * @rx_work: RX work struct to process the RX packet in @rx_skb_q
344 * @txq: TX Queue struct
345 * @rxq: RX Queue struct
352 /* lock used in MSI-X interrupt */
354 /* lock to serialize rx events */
397 return ioread32(data->base_addr + offset); in btintel_pcie_rd_reg32()
403 iowrite8(val, data->base_addr + offset); in btintel_pcie_wr_reg8()
409 iowrite32(val, data->base_addr + offset); in btintel_pcie_wr_reg32()
417 r = ioread32(data->base_addr + offset); in btintel_pcie_set_reg_bits()
419 iowrite32(r, data->base_addr + offset); in btintel_pcie_set_reg_bits()
427 r = ioread32(data->base_addr + offset); in btintel_pcie_clr_reg_bits()
429 iowrite32(r, data->base_addr + offset); in btintel_pcie_clr_reg_bits()