7  * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
19 					 u32 mask, u32 value)  in bcma_cc_write32_masked()  argument
21 	value &= mask;  in bcma_cc_write32_masked()
22 	value |= bcma_cc_read32(cc, offset) & ~mask;  in bcma_cc_write32_masked()
30 	if (cc->capabilities & BCMA_CC_CAP_PMU)  in bcma_chipco_get_alp_clock()
39 	struct bcma_bus *bus = cc->core->bus;  in bcma_core_cc_has_pmu_watchdog()
41 	if (cc->capabilities & BCMA_CC_CAP_PMU) {  in bcma_core_cc_has_pmu_watchdog()
42 		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573) {  in bcma_core_cc_has_pmu_watchdog()
43 			WARN(bus->chipinfo.rev <= 1, "No watchdog available\n");  in bcma_core_cc_has_pmu_watchdog()
58 	struct bcma_bus *bus = cc->core->bus;  in bcma_chipco_watchdog_get_max_timer()
62 		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)  in bcma_chipco_watchdog_get_max_timer()
64 		else if (cc->core->id.rev < 26)  in bcma_chipco_watchdog_get_max_timer()
67 			nb = (cc->core->id.rev >= 37) ? 32 : 24;  in bcma_chipco_watchdog_get_max_timer()
74 		return (1 << nb) - 1;  in bcma_chipco_watchdog_get_max_timer()
91 	ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);  in bcma_chipco_watchdog_timer_set_ms_wdt()
92 	return ticks / cc->ticks_per_ms;  in bcma_chipco_watchdog_timer_set_ms_wdt()
97 	struct bcma_bus *bus = cc->core->bus;  in bcma_chipco_watchdog_ticks_per_ms()
99 	if (cc->capabilities & BCMA_CC_CAP_PMU) {  in bcma_chipco_watchdog_ticks_per_ms()
100 		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)  in bcma_chipco_watchdog_ticks_per_ms()
115 	struct bcma_bus *bus = cc->core->bus;  in bcma_chipco_watchdog_register()
119 	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573 &&  in bcma_chipco_watchdog_register()
120 	    bus->chipinfo.rev <= 1) {  in bcma_chipco_watchdog_register()
129 		bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;  in bcma_chipco_watchdog_register()
131 	pdev = platform_device_register_data(NULL, "bcm47xx-wdt",  in bcma_chipco_watchdog_register()
132 					     bus->num, &wdt,  in bcma_chipco_watchdog_register()
137 	cc->watchdog = pdev;  in bcma_chipco_watchdog_register()
144 	struct bcma_bus *bus = cc->core->bus;  in bcma_core_chipcommon_flash_detect()
146 	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {  in bcma_core_chipcommon_flash_detect()
160 	if (cc->core->id.rev == 38 ||  in bcma_core_chipcommon_flash_detect()
161 	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {  in bcma_core_chipcommon_flash_detect()
162 		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {  in bcma_core_chipcommon_flash_detect()
171 	struct bcma_bus *bus = cc->core->bus;  in bcma_core_chipcommon_early_init()
173 	if (cc->early_setup_done)  in bcma_core_chipcommon_early_init()
176 	spin_lock_init(&cc->gpio_lock);  in bcma_core_chipcommon_early_init()
178 	if (cc->core->id.rev >= 11)  in bcma_core_chipcommon_early_init()
179 		cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);  in bcma_core_chipcommon_early_init()
180 	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);  in bcma_core_chipcommon_early_init()
181 	if (cc->core->id.rev >= 35)  in bcma_core_chipcommon_early_init()
182 		cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);  in bcma_core_chipcommon_early_init()
184 	if (cc->capabilities & BCMA_CC_CAP_PMU)  in bcma_core_chipcommon_early_init()
187 	if (bus->hosttype == BCMA_HOSTTYPE_SOC)  in bcma_core_chipcommon_early_init()
190 	cc->early_setup_done = true;  in bcma_core_chipcommon_early_init()
198 	if (cc->setup_done)  in bcma_core_chipcommon_init()
203 	if (cc->core->id.rev >= 20) {  in bcma_core_chipcommon_init()
206 		if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {  in bcma_core_chipcommon_init()
215 	if (cc->capabilities & BCMA_CC_CAP_PMU)  in bcma_core_chipcommon_init()
217 	if (cc->capabilities & BCMA_CC_CAP_PCTL)  in bcma_core_chipcommon_init()
218 		bcma_err(cc->core->bus, "Power control not implemented!\n");  in bcma_core_chipcommon_init()
220 	if (cc->core->id.rev >= 16) {  in bcma_core_chipcommon_init()
221 		if (cc->core->bus->sprom.leddc_on_time &&  in bcma_core_chipcommon_init()
222 		    cc->core->bus->sprom.leddc_off_time) {  in bcma_core_chipcommon_init()
223 			leddc_on = cc->core->bus->sprom.leddc_on_time;  in bcma_core_chipcommon_init()
224 			leddc_off = cc->core->bus->sprom.leddc_off_time;  in bcma_core_chipcommon_init()
230 	cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);  in bcma_core_chipcommon_init()
232 	cc->setup_done = true;  in bcma_core_chipcommon_init()
248 		struct bcma_bus *bus = cc->core->bus;  in bcma_chipco_watchdog_timer_set()
250 		if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&  in bcma_chipco_watchdog_timer_set()
251 		    bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&  in bcma_chipco_watchdog_timer_set()
252 		    bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)  in bcma_chipco_watchdog_timer_set()
253 			bcma_core_set_clockmode(cc->core,  in bcma_chipco_watchdog_timer_set()
264 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_irq_mask()  argument
266 	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);  in bcma_chipco_irq_mask()
269 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)  in bcma_chipco_irq_status()  argument
271 	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;  in bcma_chipco_irq_status()
274 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)  in bcma_chipco_gpio_in()  argument
276 	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;  in bcma_chipco_gpio_in()
279 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_out()  argument
281 	unsigned long flags;  in bcma_chipco_gpio_out()  local
284 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_out()
285 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);  in bcma_chipco_gpio_out()
286 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_out()
292 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_outen()  argument
294 	unsigned long flags;  in bcma_chipco_gpio_outen()  local
297 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_outen()
298 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);  in bcma_chipco_gpio_outen()
299 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_outen()
309 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_control()  argument
311 	unsigned long flags;  in bcma_chipco_gpio_control()  local
314 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_control()
315 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);  in bcma_chipco_gpio_control()
316 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_control()
322 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_intmask()  argument
324 	unsigned long flags;  in bcma_chipco_gpio_intmask()  local
327 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_intmask()
328 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);  in bcma_chipco_gpio_intmask()
329 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_intmask()
334 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_polarity()  argument
336 	unsigned long flags;  in bcma_chipco_gpio_polarity()  local
339 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_polarity()
340 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);  in bcma_chipco_gpio_polarity()
341 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_polarity()
346 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_pullup()  argument
348 	unsigned long flags;  in bcma_chipco_gpio_pullup()  local
351 	if (cc->core->id.rev < 20)  in bcma_chipco_gpio_pullup()
354 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_pullup()
355 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);  in bcma_chipco_gpio_pullup()
356 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_pullup()
361 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)  in bcma_chipco_gpio_pulldown()  argument
363 	unsigned long flags;  in bcma_chipco_gpio_pulldown()  local
366 	if (cc->core->id.rev < 20)  in bcma_chipco_gpio_pulldown()
369 	spin_lock_irqsave(&cc->gpio_lock, flags);  in bcma_chipco_gpio_pulldown()
370 	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);  in bcma_chipco_gpio_pulldown()
371 	spin_unlock_irqrestore(&cc->gpio_lock, flags);  in bcma_chipco_gpio_pulldown()
382 	unsigned int ccrev = cc->core->id.rev;  in bcma_chipco_serial_init()
383 	struct bcma_serial_port *ports = cc->serial_ports;  in bcma_chipco_serial_init()
398 			/* Re-enable the UART clock. */  in bcma_chipco_serial_init()
404 		bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",  in bcma_chipco_serial_init()
409 	irq = bcma_core_irq(cc->core, 0);  in bcma_chipco_serial_init()
412 	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);  in bcma_chipco_serial_init()
413 	for (i = 0; i < cc->nr_serial_ports; i++) {  in bcma_chipco_serial_init()
414 		ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +  in bcma_chipco_serial_init()