Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - MMIO support
18 void __iomem *regs; member
39 return -EINVAL; in regmap_mmio_regbits_check()
59 return -EINVAL; in regmap_mmio_get_min_stride()
69 writeb(val, ctx->regs + reg); in regmap_mmio_write8()
76 writeb_relaxed(val, ctx->regs + reg); in regmap_mmio_write8_relaxed()
82 iowrite8(val, ctx->regs + reg); in regmap_mmio_iowrite8()
89 writew(val, ctx->regs + reg); in regmap_mmio_write16le()
96 writew_relaxed(val, ctx->regs + reg); in regmap_mmio_write16le_relaxed()
102 iowrite16(val, ctx->regs + reg); in regmap_mmio_iowrite16le()
109 writew(swab16(val), ctx->regs + reg); in regmap_mmio_write16be()
115 iowrite16be(val, ctx->regs + reg); in regmap_mmio_iowrite16be()
122 writel(val, ctx->regs + reg); in regmap_mmio_write32le()
129 writel_relaxed(val, ctx->regs + reg); in regmap_mmio_write32le_relaxed()
135 iowrite32(val, ctx->regs + reg); in regmap_mmio_iowrite32le()
142 writel(swab32(val), ctx->regs + reg); in regmap_mmio_write32be()
148 iowrite32be(val, ctx->regs + reg); in regmap_mmio_iowrite32be()
156 if (!IS_ERR(ctx->clk)) { in regmap_mmio_write()
157 ret = clk_enable(ctx->clk); in regmap_mmio_write()
162 ctx->reg_write(ctx, reg, val); in regmap_mmio_write()
164 if (!IS_ERR(ctx->clk)) in regmap_mmio_write()
165 clk_disable(ctx->clk); in regmap_mmio_write()
177 if (!IS_ERR(ctx->clk)) { in regmap_mmio_noinc_write()
178 ret = clk_enable(ctx->clk); in regmap_mmio_noinc_write()
184 * There are no native, assembly-optimized write single register in regmap_mmio_noinc_write()
185 * operations for big endian, so fall back to emulation if this in regmap_mmio_noinc_write()
189 if (ctx->big_endian && (ctx->val_bytes > 1)) { in regmap_mmio_noinc_write()
190 switch (ctx->val_bytes) { in regmap_mmio_noinc_write()
195 writew(swab16(valp[i]), ctx->regs + reg); in regmap_mmio_noinc_write()
202 writel(swab32(valp[i]), ctx->regs + reg); in regmap_mmio_noinc_write()
206 ret = -EINVAL; in regmap_mmio_noinc_write()
211 switch (ctx->val_bytes) { in regmap_mmio_noinc_write()
213 writesb(ctx->regs + reg, (const u8 *)val, val_count); in regmap_mmio_noinc_write()
216 writesw(ctx->regs + reg, (const u16 *)val, val_count); in regmap_mmio_noinc_write()
219 writesl(ctx->regs + reg, (const u32 *)val, val_count); in regmap_mmio_noinc_write()
222 ret = -EINVAL; in regmap_mmio_noinc_write()
227 if (!IS_ERR(ctx->clk)) in regmap_mmio_noinc_write()
228 clk_disable(ctx->clk); in regmap_mmio_noinc_write()
236 return readb(ctx->regs + reg); in regmap_mmio_read8()
242 return readb_relaxed(ctx->regs + reg); in regmap_mmio_read8_relaxed()
248 return ioread8(ctx->regs + reg); in regmap_mmio_ioread8()
254 return readw(ctx->regs + reg); in regmap_mmio_read16le()
260 return readw_relaxed(ctx->regs + reg); in regmap_mmio_read16le_relaxed()
266 return ioread16(ctx->regs + reg); in regmap_mmio_ioread16le()
272 return swab16(readw(ctx->regs + reg)); in regmap_mmio_read16be()
278 return ioread16be(ctx->regs + reg); in regmap_mmio_ioread16be()
284 return readl(ctx->regs + reg); in regmap_mmio_read32le()
290 return readl_relaxed(ctx->regs + reg); in regmap_mmio_read32le_relaxed()
296 return ioread32(ctx->regs + reg); in regmap_mmio_ioread32le()
302 return swab32(readl(ctx->regs + reg)); in regmap_mmio_read32be()
308 return ioread32be(ctx->regs + reg); in regmap_mmio_ioread32be()
316 if (!IS_ERR(ctx->clk)) { in regmap_mmio_read()
317 ret = clk_enable(ctx->clk); in regmap_mmio_read()
322 *val = ctx->reg_read(ctx, reg); in regmap_mmio_read()
324 if (!IS_ERR(ctx->clk)) in regmap_mmio_read()
325 clk_disable(ctx->clk); in regmap_mmio_read()
336 if (!IS_ERR(ctx->clk)) { in regmap_mmio_noinc_read()
337 ret = clk_enable(ctx->clk); in regmap_mmio_noinc_read()
342 switch (ctx->val_bytes) { in regmap_mmio_noinc_read()
344 readsb(ctx->regs + reg, (u8 *)val, val_count); in regmap_mmio_noinc_read()
347 readsw(ctx->regs + reg, (u16 *)val, val_count); in regmap_mmio_noinc_read()
350 readsl(ctx->regs + reg, (u32 *)val, val_count); in regmap_mmio_noinc_read()
353 ret = -EINVAL; in regmap_mmio_noinc_read()
358 * There are no native, assembly-optimized write single register in regmap_mmio_noinc_read()
359 * operations for big endian, so fall back to emulation if this in regmap_mmio_noinc_read()
363 if (ctx->big_endian && (ctx->val_bytes > 1)) { in regmap_mmio_noinc_read()
364 switch (ctx->val_bytes) { in regmap_mmio_noinc_read()
372 ret = -EINVAL; in regmap_mmio_noinc_read()
378 if (!IS_ERR(ctx->clk)) in regmap_mmio_noinc_read()
379 clk_disable(ctx->clk); in regmap_mmio_noinc_read()
389 if (!IS_ERR(ctx->clk)) { in regmap_mmio_free_context()
390 clk_unprepare(ctx->clk); in regmap_mmio_free_context()
391 if (!ctx->attached_clk) in regmap_mmio_free_context()
392 clk_put(ctx->clk); in regmap_mmio_free_context()
409 void __iomem *regs, in regmap_mmio_gen_context() argument
416 ret = regmap_mmio_regbits_check(config->reg_bits); in regmap_mmio_gen_context()
420 if (config->pad_bits) in regmap_mmio_gen_context()
421 return ERR_PTR(-EINVAL); in regmap_mmio_gen_context()
423 min_stride = regmap_mmio_get_min_stride(config->val_bits); in regmap_mmio_gen_context()
427 if (config->reg_stride && config->reg_stride < min_stride) in regmap_mmio_gen_context()
428 return ERR_PTR(-EINVAL); in regmap_mmio_gen_context()
430 if (config->use_relaxed_mmio && config->io_port) in regmap_mmio_gen_context()
431 return ERR_PTR(-EINVAL); in regmap_mmio_gen_context()
435 return ERR_PTR(-ENOMEM); in regmap_mmio_gen_context()
437 ctx->regs = regs; in regmap_mmio_gen_context()
438 ctx->val_bytes = config->val_bits / 8; in regmap_mmio_gen_context()
439 ctx->clk = ERR_PTR(-ENODEV); in regmap_mmio_gen_context()
447 switch (config->val_bits) { in regmap_mmio_gen_context()
449 if (config->io_port) { in regmap_mmio_gen_context()
450 ctx->reg_read = regmap_mmio_ioread8; in regmap_mmio_gen_context()
451 ctx->reg_write = regmap_mmio_iowrite8; in regmap_mmio_gen_context()
452 } else if (config->use_relaxed_mmio) { in regmap_mmio_gen_context()
453 ctx->reg_read = regmap_mmio_read8_relaxed; in regmap_mmio_gen_context()
454 ctx->reg_write = regmap_mmio_write8_relaxed; in regmap_mmio_gen_context()
456 ctx->reg_read = regmap_mmio_read8; in regmap_mmio_gen_context()
457 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context()
461 if (config->io_port) { in regmap_mmio_gen_context()
462 ctx->reg_read = regmap_mmio_ioread16le; in regmap_mmio_gen_context()
463 ctx->reg_write = regmap_mmio_iowrite16le; in regmap_mmio_gen_context()
464 } else if (config->use_relaxed_mmio) { in regmap_mmio_gen_context()
465 ctx->reg_read = regmap_mmio_read16le_relaxed; in regmap_mmio_gen_context()
466 ctx->reg_write = regmap_mmio_write16le_relaxed; in regmap_mmio_gen_context()
468 ctx->reg_read = regmap_mmio_read16le; in regmap_mmio_gen_context()
469 ctx->reg_write = regmap_mmio_write16le; in regmap_mmio_gen_context()
473 if (config->io_port) { in regmap_mmio_gen_context()
474 ctx->reg_read = regmap_mmio_ioread32le; in regmap_mmio_gen_context()
475 ctx->reg_write = regmap_mmio_iowrite32le; in regmap_mmio_gen_context()
476 } else if (config->use_relaxed_mmio) { in regmap_mmio_gen_context()
477 ctx->reg_read = regmap_mmio_read32le_relaxed; in regmap_mmio_gen_context()
478 ctx->reg_write = regmap_mmio_write32le_relaxed; in regmap_mmio_gen_context()
480 ctx->reg_read = regmap_mmio_read32le; in regmap_mmio_gen_context()
481 ctx->reg_write = regmap_mmio_write32le; in regmap_mmio_gen_context()
485 ret = -EINVAL; in regmap_mmio_gen_context()
493 ctx->big_endian = true; in regmap_mmio_gen_context()
494 switch (config->val_bits) { in regmap_mmio_gen_context()
496 if (config->io_port) { in regmap_mmio_gen_context()
497 ctx->reg_read = regmap_mmio_ioread8; in regmap_mmio_gen_context()
498 ctx->reg_write = regmap_mmio_iowrite8; in regmap_mmio_gen_context()
500 ctx->reg_read = regmap_mmio_read8; in regmap_mmio_gen_context()
501 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context()
505 if (config->io_port) { in regmap_mmio_gen_context()
506 ctx->reg_read = regmap_mmio_ioread16be; in regmap_mmio_gen_context()
507 ctx->reg_write = regmap_mmio_iowrite16be; in regmap_mmio_gen_context()
509 ctx->reg_read = regmap_mmio_read16be; in regmap_mmio_gen_context()
510 ctx->reg_write = regmap_mmio_write16be; in regmap_mmio_gen_context()
514 if (config->io_port) { in regmap_mmio_gen_context()
515 ctx->reg_read = regmap_mmio_ioread32be; in regmap_mmio_gen_context()
516 ctx->reg_write = regmap_mmio_iowrite32be; in regmap_mmio_gen_context()
518 ctx->reg_read = regmap_mmio_read32be; in regmap_mmio_gen_context()
519 ctx->reg_write = regmap_mmio_write32be; in regmap_mmio_gen_context()
523 ret = -EINVAL; in regmap_mmio_gen_context()
528 ret = -EINVAL; in regmap_mmio_gen_context()
535 ctx->clk = clk_get(dev, clk_id); in regmap_mmio_gen_context()
536 if (IS_ERR(ctx->clk)) { in regmap_mmio_gen_context()
537 ret = PTR_ERR(ctx->clk); in regmap_mmio_gen_context()
541 ret = clk_prepare(ctx->clk); in regmap_mmio_gen_context()
543 clk_put(ctx->clk); in regmap_mmio_gen_context()
556 void __iomem *regs, in __regmap_init_mmio_clk() argument
563 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config); in __regmap_init_mmio_clk()
574 void __iomem *regs, in __devm_regmap_init_mmio_clk() argument
581 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config); in __devm_regmap_init_mmio_clk()
592 struct regmap_mmio_context *ctx = map->bus_context; in regmap_mmio_attach_clk()
594 ctx->clk = clk; in regmap_mmio_attach_clk()
595 ctx->attached_clk = true; in regmap_mmio_attach_clk()
597 return clk_prepare(ctx->clk); in regmap_mmio_attach_clk()
603 struct regmap_mmio_context *ctx = map->bus_context; in regmap_mmio_detach_clk()
605 clk_unprepare(ctx->clk); in regmap_mmio_detach_clk()
607 ctx->attached_clk = false; in regmap_mmio_detach_clk()
608 ctx->clk = NULL; in regmap_mmio_detach_clk()