Lines Matching +full:int +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
24 struct regmap *map; member
27 int irq_base;
30 int irq;
31 int wake_count;
34 unsigned int *main_status_buf;
35 unsigned int *status_buf;
36 unsigned int *mask_buf;
37 unsigned int *mask_buf_def;
38 unsigned int *wake_buf;
39 unsigned int *type_buf;
40 unsigned int *type_buf_def;
41 unsigned int **config_buf;
43 unsigned int irq_reg_stride;
45 unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data,
46 unsigned int base, int index);
48 unsigned int clear_status:1;
53 int irq) in irq_to_regmap_irq()
55 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
60 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status() local
63 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
67 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
68 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
69 !map->use_single_read; in regmap_irq_can_bulk_read_status()
76 mutex_lock(&d->lock); in regmap_irq_lock()
82 struct regmap *map = d->map; in regmap_irq_sync_unlock() local
83 int i, j, ret; in regmap_irq_sync_unlock()
87 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
88 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
90 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
94 if (d->clear_status) { in regmap_irq_sync_unlock()
95 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
96 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
98 ret = regmap_read(map, reg, &val); in regmap_irq_sync_unlock()
100 dev_err(d->map->dev, in regmap_irq_sync_unlock()
104 d->clear_status = false; in regmap_irq_sync_unlock()
108 * If there's been a change in the mask write it back to the in regmap_irq_sync_unlock()
112 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
113 if (d->chip->handle_mask_sync) in regmap_irq_sync_unlock()
114 d->chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_irq_sync_unlock()
115 d->mask_buf[i], in regmap_irq_sync_unlock()
116 d->chip->irq_drv_data); in regmap_irq_sync_unlock()
118 if (d->chip->mask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
119 reg = d->get_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
120 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
121 d->mask_buf_def[i], in regmap_irq_sync_unlock()
122 d->mask_buf[i]); in regmap_irq_sync_unlock()
124 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); in regmap_irq_sync_unlock()
127 if (d->chip->unmask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
128 reg = d->get_irq_reg(d, d->chip->unmask_base, i); in regmap_irq_sync_unlock()
129 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
130 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
132 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
136 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
137 if (d->wake_buf) { in regmap_irq_sync_unlock()
138 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
139 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
140 d->mask_buf_def[i], in regmap_irq_sync_unlock()
141 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
143 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
144 d->mask_buf_def[i], in regmap_irq_sync_unlock()
145 d->wake_buf[i]); in regmap_irq_sync_unlock()
147 dev_err(d->map->dev, in regmap_irq_sync_unlock()
152 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
159 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
160 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
163 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
164 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
166 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
167 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
168 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
169 ret = regmap_write(map, reg, UINT_MAX); in regmap_irq_sync_unlock()
171 ret = regmap_write(map, reg, 0); in regmap_irq_sync_unlock()
174 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
179 for (i = 0; i < d->chip->num_config_bases; i++) { in regmap_irq_sync_unlock()
180 for (j = 0; j < d->chip->num_config_regs; j++) { in regmap_irq_sync_unlock()
181 reg = d->get_irq_reg(d, d->chip->config_base[i], j); in regmap_irq_sync_unlock()
182 ret = regmap_write(map, reg, d->config_buf[i][j]); in regmap_irq_sync_unlock()
184 dev_err(d->map->dev, in regmap_irq_sync_unlock()
190 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
191 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
194 if (d->wake_count < 0) in regmap_irq_sync_unlock()
195 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
196 irq_set_irq_wake(d->irq, 0); in regmap_irq_sync_unlock()
197 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
198 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
199 irq_set_irq_wake(d->irq, 1); in regmap_irq_sync_unlock()
201 d->wake_count = 0; in regmap_irq_sync_unlock()
203 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
209 struct regmap *map = d->map; in regmap_irq_enable() local
210 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
211 unsigned int reg = irq_data->reg_offset / map->reg_stride; in regmap_irq_enable()
212 unsigned int mask; in regmap_irq_enable() local
216 * separate mask bits for each interrupt trigger type, but we want in regmap_irq_enable()
220 * then instead of using the regular mask bits for this interrupt, in regmap_irq_enable()
224 if (d->chip->type_in_mask && irq_data->type.types_supported) in regmap_irq_enable()
225 mask = d->type_buf[reg] & irq_data->mask; in regmap_irq_enable()
227 mask = irq_data->mask; in regmap_irq_enable()
229 if (d->chip->clear_on_unmask) in regmap_irq_enable()
230 d->clear_status = true; in regmap_irq_enable()
232 d->mask_buf[reg] &= ~mask; in regmap_irq_enable()
238 struct regmap *map = d->map; in regmap_irq_disable() local
239 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
241 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
244 static int regmap_irq_set_type(struct irq_data *data, unsigned int type) in regmap_irq_set_type()
247 struct regmap *map = d->map; in regmap_irq_set_type() local
248 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
249 int reg, ret; in regmap_irq_set_type()
250 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
252 if ((t->types_supported & type) != type) in regmap_irq_set_type()
255 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
257 if (d->chip->type_in_mask) { in regmap_irq_set_type()
258 ret = regmap_irq_set_type_config_simple(&d->type_buf, type, in regmap_irq_set_type()
259 irq_data, reg, d->chip->irq_drv_data); in regmap_irq_set_type()
264 if (d->chip->set_type_config) { in regmap_irq_set_type()
265 ret = d->chip->set_type_config(d->config_buf, type, irq_data, in regmap_irq_set_type()
266 reg, d->chip->irq_drv_data); in regmap_irq_set_type()
274 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) in regmap_irq_set_wake()
277 struct regmap *map = d->map; in regmap_irq_set_wake() local
278 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
281 if (d->wake_buf) in regmap_irq_set_wake()
282 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
283 &= ~irq_data->mask; in regmap_irq_set_wake()
284 d->wake_count++; in regmap_irq_set_wake()
286 if (d->wake_buf) in regmap_irq_set_wake()
287 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
288 |= irq_data->mask; in regmap_irq_set_wake()
289 d->wake_count--; in regmap_irq_set_wake()
304 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, in read_sub_irq_data()
305 unsigned int b) in read_sub_irq_data()
307 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data()
309 struct regmap *map = data->map; in read_sub_irq_data() local
310 unsigned int reg; in read_sub_irq_data()
311 int i, ret = 0; in read_sub_irq_data()
313 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
314 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
315 ret = regmap_read(map, reg, &data->status_buf[b]); in read_sub_irq_data()
318 * Note we can't use ->get_irq_reg() here because the offsets in read_sub_irq_data()
321 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
322 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
323 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
324 unsigned int index = offset / map->reg_stride; in read_sub_irq_data()
326 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
327 &data->status_buf[index]); in read_sub_irq_data()
335 static irqreturn_t regmap_irq_thread(int irq, void *d) in regmap_irq_thread()
338 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread()
339 struct regmap *map = data->map; in regmap_irq_thread() local
340 int ret, i; in regmap_irq_thread()
344 if (chip->handle_pre_irq) in regmap_irq_thread()
345 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
347 if (chip->runtime_pm) { in regmap_irq_thread()
348 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
350 dev_err(map->dev, "IRQ thread failed to resume: %d\n", in regmap_irq_thread()
362 if (chip->no_status) { in regmap_irq_thread()
364 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs); in regmap_irq_thread()
365 } else if (chip->num_main_regs) { in regmap_irq_thread()
366 unsigned int max_main_bits; in regmap_irq_thread()
369 size = chip->num_regs * sizeof(unsigned int); in regmap_irq_thread()
371 max_main_bits = (chip->num_main_status_bits) ? in regmap_irq_thread()
372 chip->num_main_status_bits : chip->num_regs; in regmap_irq_thread()
374 memset(data->status_buf, 0, size); in regmap_irq_thread()
381 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
382 reg = data->get_irq_reg(data, chip->main_status, i); in regmap_irq_thread()
383 ret = regmap_read(map, reg, &data->main_status_buf[i]); in regmap_irq_thread()
385 dev_err(map->dev, in regmap_irq_thread()
393 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
394 unsigned int b; in regmap_irq_thread()
395 const unsigned long mreg = data->main_status_buf[i]; in regmap_irq_thread()
397 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in regmap_irq_thread()
398 if (i * map->format.val_bytes * 8 + b > in regmap_irq_thread()
404 dev_err(map->dev, in regmap_irq_thread()
414 u8 *buf8 = data->status_reg_buf; in regmap_irq_thread()
415 u16 *buf16 = data->status_reg_buf; in regmap_irq_thread()
416 u32 *buf32 = data->status_reg_buf; in regmap_irq_thread()
418 BUG_ON(!data->status_reg_buf); in regmap_irq_thread()
420 ret = regmap_bulk_read(map, chip->status_base, in regmap_irq_thread()
421 data->status_reg_buf, in regmap_irq_thread()
422 chip->num_regs); in regmap_irq_thread()
424 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_irq_thread()
429 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
430 switch (map->format.val_bytes) { in regmap_irq_thread()
432 data->status_buf[i] = buf8[i]; in regmap_irq_thread()
435 data->status_buf[i] = buf16[i]; in regmap_irq_thread()
438 data->status_buf[i] = buf32[i]; in regmap_irq_thread()
447 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
448 unsigned int reg = data->get_irq_reg(data, in regmap_irq_thread()
449 data->chip->status_base, i); in regmap_irq_thread()
450 ret = regmap_read(map, reg, &data->status_buf[i]); in regmap_irq_thread()
453 dev_err(map->dev, in regmap_irq_thread()
461 if (chip->status_invert) in regmap_irq_thread()
462 for (i = 0; i < data->chip->num_regs; i++) in regmap_irq_thread()
463 data->status_buf[i] = ~data->status_buf[i]; in regmap_irq_thread()
472 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
473 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
475 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
476 reg = data->get_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
478 if (chip->ack_invert) in regmap_irq_thread()
479 ret = regmap_write(map, reg, in regmap_irq_thread()
480 ~data->status_buf[i]); in regmap_irq_thread()
482 ret = regmap_write(map, reg, in regmap_irq_thread()
483 data->status_buf[i]); in regmap_irq_thread()
484 if (chip->clear_ack) { in regmap_irq_thread()
485 if (chip->ack_invert && !ret) in regmap_irq_thread()
486 ret = regmap_write(map, reg, UINT_MAX); in regmap_irq_thread()
488 ret = regmap_write(map, reg, 0); in regmap_irq_thread()
491 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
496 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
497 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
498 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
499 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
505 if (chip->handle_post_irq) in regmap_irq_thread()
506 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
508 if (chip->runtime_pm) in regmap_irq_thread()
509 pm_runtime_put(map->dev); in regmap_irq_thread()
517 static int regmap_irq_map(struct irq_domain *h, unsigned int virq, in regmap_irq_map()
520 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
523 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
525 irq_set_parent(virq, data->irq); in regmap_irq_map()
532 .map = regmap_irq_map,
537 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
545 unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, in regmap_irq_get_irq_reg_linear()
546 unsigned int base, int index) in regmap_irq_get_irq_reg_linear()
548 struct regmap *map = data->map; in regmap_irq_get_irq_reg_linear() local
550 return base + index * map->reg_stride * data->irq_reg_stride; in regmap_irq_get_irq_reg_linear()
555 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
563 * This is a &struct regmap_irq_chip->set_type_config callback suitable for
567 int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, in regmap_irq_set_type_config_simple()
569 int idx, void *irq_drv_data) in regmap_irq_set_type_config_simple()
571 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type_config_simple()
573 if (t->type_reg_mask) in regmap_irq_set_type_config_simple()
574 buf[0][idx] &= ~t->type_reg_mask; in regmap_irq_set_type_config_simple()
576 buf[0][idx] &= ~(t->type_falling_val | in regmap_irq_set_type_config_simple()
577 t->type_rising_val | in regmap_irq_set_type_config_simple()
578 t->type_level_low_val | in regmap_irq_set_type_config_simple()
579 t->type_level_high_val); in regmap_irq_set_type_config_simple()
583 buf[0][idx] |= t->type_falling_val; in regmap_irq_set_type_config_simple()
587 buf[0][idx] |= t->type_rising_val; in regmap_irq_set_type_config_simple()
591 buf[0][idx] |= (t->type_falling_val | in regmap_irq_set_type_config_simple()
592 t->type_rising_val); in regmap_irq_set_type_config_simple()
596 buf[0][idx] |= t->type_level_high_val; in regmap_irq_set_type_config_simple()
600 buf[0][idx] |= t->type_level_low_val; in regmap_irq_set_type_config_simple()
604 return -EINVAL; in regmap_irq_set_type_config_simple()
611 static int regmap_irq_create_domain(struct fwnode_handle *fwnode, int irq_base, in regmap_irq_create_domain()
617 .size = chip->num_irqs, in regmap_irq_create_domain()
618 .hwirq_max = chip->num_irqs, in regmap_irq_create_domain()
622 .name_suffix = chip->domain_suffix, in regmap_irq_create_domain()
625 d->domain = irq_domain_instantiate(&info); in regmap_irq_create_domain()
626 if (IS_ERR(d->domain)) { in regmap_irq_create_domain()
627 dev_err(d->map->dev, "Failed to create IRQ domain\n"); in regmap_irq_create_domain()
628 return PTR_ERR(d->domain); in regmap_irq_create_domain()
636 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
639 * @map: The regmap for the device.
652 int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, in regmap_add_irq_chip_fwnode()
653 struct regmap *map, int irq, in regmap_add_irq_chip_fwnode() argument
654 int irq_flags, int irq_base, in regmap_add_irq_chip_fwnode()
659 int i; in regmap_add_irq_chip_fwnode()
660 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
663 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
664 return -EINVAL; in regmap_add_irq_chip_fwnode()
666 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
667 return -EINVAL; in regmap_add_irq_chip_fwnode()
669 if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted) in regmap_add_irq_chip_fwnode()
670 return -EINVAL; in regmap_add_irq_chip_fwnode()
672 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
673 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
674 return -EINVAL; in regmap_add_irq_chip_fwnode()
675 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
676 chip->num_regs) in regmap_add_irq_chip_fwnode()
677 return -EINVAL; in regmap_add_irq_chip_fwnode()
681 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
683 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
691 return -ENOMEM; in regmap_add_irq_chip_fwnode()
693 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
694 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
695 sizeof(*d->main_status_buf), in regmap_add_irq_chip_fwnode()
698 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
702 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), in regmap_add_irq_chip_fwnode()
704 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
707 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), in regmap_add_irq_chip_fwnode()
709 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
712 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), in regmap_add_irq_chip_fwnode()
714 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
717 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
718 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), in regmap_add_irq_chip_fwnode()
720 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
724 if (chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
725 d->type_buf_def = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
726 sizeof(*d->type_buf_def), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
727 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
730 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
731 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
735 if (chip->num_config_bases && chip->num_config_regs) { in regmap_add_irq_chip_fwnode()
739 d->config_buf = kcalloc(chip->num_config_bases, in regmap_add_irq_chip_fwnode()
740 sizeof(*d->config_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
741 if (!d->config_buf) in regmap_add_irq_chip_fwnode()
744 for (i = 0; i < chip->num_config_bases; i++) { in regmap_add_irq_chip_fwnode()
745 d->config_buf[i] = kcalloc(chip->num_config_regs, in regmap_add_irq_chip_fwnode()
746 sizeof(**d->config_buf), in regmap_add_irq_chip_fwnode()
748 if (!d->config_buf[i]) in regmap_add_irq_chip_fwnode()
753 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
754 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
755 d->irq = irq; in regmap_add_irq_chip_fwnode()
756 d->map = map; in regmap_add_irq_chip_fwnode()
757 d->chip = chip; in regmap_add_irq_chip_fwnode()
758 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
760 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
761 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
763 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
765 if (chip->get_irq_reg) in regmap_add_irq_chip_fwnode()
766 d->get_irq_reg = chip->get_irq_reg; in regmap_add_irq_chip_fwnode()
768 d->get_irq_reg = regmap_irq_get_irq_reg_linear; in regmap_add_irq_chip_fwnode()
771 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
772 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
774 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
778 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
780 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
781 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
782 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
784 /* Mask all the interrupts by default */ in regmap_add_irq_chip_fwnode()
785 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
786 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
788 if (chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
789 ret = chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
790 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
791 chip->irq_drv_data); in regmap_add_irq_chip_fwnode()
796 if (chip->mask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
797 reg = d->get_irq_reg(d, chip->mask_base, i); in regmap_add_irq_chip_fwnode()
798 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
799 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
800 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
802 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
808 if (chip->unmask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
809 reg = d->get_irq_reg(d, chip->unmask_base, i); in regmap_add_irq_chip_fwnode()
810 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
811 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
813 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
819 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
823 if (d->chip->no_status) { in regmap_add_irq_chip_fwnode()
825 d->status_buf[i] = GENMASK(31, 0); in regmap_add_irq_chip_fwnode()
827 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
828 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
830 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
836 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
837 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
839 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
840 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
841 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
842 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
843 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
845 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
846 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
847 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
848 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
849 ret = regmap_write(map, reg, UINT_MAX); in regmap_add_irq_chip_fwnode()
851 ret = regmap_write(map, reg, 0); in regmap_add_irq_chip_fwnode()
854 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
862 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
863 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
864 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
865 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
867 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
868 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
869 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
872 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
873 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
874 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
876 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
889 chip->name, d); in regmap_add_irq_chip_fwnode()
891 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
892 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
903 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
904 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
905 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
906 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
907 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
908 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
909 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
910 if (d->config_buf) { in regmap_add_irq_chip_fwnode()
911 for (i = 0; i < chip->num_config_bases; i++) in regmap_add_irq_chip_fwnode()
912 kfree(d->config_buf[i]); in regmap_add_irq_chip_fwnode()
913 kfree(d->config_buf); in regmap_add_irq_chip_fwnode()
921 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
923 * @map: The regmap for the device.
935 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, in regmap_add_irq_chip() argument
936 int irq_base, const struct regmap_irq_chip *chip, in regmap_add_irq_chip()
939 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
945 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
952 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) in regmap_del_irq_chip()
954 unsigned int virq; in regmap_del_irq_chip()
955 int i, hwirq; in regmap_del_irq_chip()
963 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
965 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
972 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
977 irq_domain_remove(d->domain); in regmap_del_irq_chip()
978 kfree(d->type_buf); in regmap_del_irq_chip()
979 kfree(d->type_buf_def); in regmap_del_irq_chip()
980 kfree(d->wake_buf); in regmap_del_irq_chip()
981 kfree(d->mask_buf_def); in regmap_del_irq_chip()
982 kfree(d->mask_buf); in regmap_del_irq_chip()
983 kfree(d->status_reg_buf); in regmap_del_irq_chip()
984 kfree(d->status_buf); in regmap_del_irq_chip()
985 if (d->config_buf) { in regmap_del_irq_chip()
986 for (i = 0; i < d->chip->num_config_bases; i++) in regmap_del_irq_chip()
987 kfree(d->config_buf[i]); in regmap_del_irq_chip()
988 kfree(d->config_buf); in regmap_del_irq_chip()
998 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1001 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data) in devm_regmap_irq_chip_match()
1014 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1018 * @map: The regmap for the device.
1030 int devm_regmap_add_irq_chip_fwnode(struct device *dev, in devm_regmap_add_irq_chip_fwnode()
1032 struct regmap *map, int irq, in devm_regmap_add_irq_chip_fwnode() argument
1033 int irq_flags, int irq_base, in devm_regmap_add_irq_chip_fwnode()
1038 int ret; in devm_regmap_add_irq_chip_fwnode()
1043 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1045 ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base, in devm_regmap_add_irq_chip_fwnode()
1060 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1063 * @map: The regmap for the device.
1075 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq, in devm_regmap_add_irq_chip() argument
1076 int irq_flags, int irq_base, in devm_regmap_add_irq_chip()
1080 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1087 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1095 void devm_regmap_del_irq_chip(struct device *dev, int irq, in devm_regmap_del_irq_chip()
1098 int rc; in devm_regmap_del_irq_chip()
1100 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1110 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1116 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data) in regmap_irq_chip_get_base()
1118 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1119 return data->irq_base; in regmap_irq_chip_get_base()
1124 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1131 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq) in regmap_irq_get_virq()
1134 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1135 return -EINVAL; in regmap_irq_get_virq()
1137 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1142 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1154 return data->domain; in regmap_irq_get_domain()