Lines Matching +full:1 +full:x
55 #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1)) argument
59 #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1)) argument
63 #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1)) argument
68 #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1)) argument
95 (((unsigned long)base)|(((unsigned long)(tail+1))&mask))
99 #define ITYPE_TPD_COMPLETE (1<<3)
109 #define ITYPE_GROUP(x) (x & 0x7) argument
110 #define ITYPE_TYPE(x) (x & 0xf8) argument
144 #define TPD_ADDR(x) ((x) & TPD_MASK) argument
145 #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT) argument
157 #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3))
158 #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1))
170 #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5))
171 #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4))
172 #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3))
173 #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2))
174 #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1))
175 #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1)
190 #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */
335 #define INT_PROC_ENBL (1<<25)
336 #define SLAVE_ENDIAN_MODE (1<<16)
337 #define MRL_ENB (1<<5)
338 #define MRM_ENB (1<<4)
339 #define INIT_ENB (1<<2)
340 #define IGNORE_TIMEOUT (1<<1)
341 #define ENBL_64 (1<<0)
353 #define BOARD_RST_STATUS (1<<6)
356 #define PCI_BUS_SIZE64 (1<<27)
357 #define DESC_RD_STATIC_64 (1<<26)
358 #define DATA_RD_STATIC_64 (1<<25)
359 #define DATA_WR_STATIC_64 (1<<24)
360 #define ID_CS (1<<12)
361 #define ID_WREN (1<<11)
362 #define ID_DOUT (1<<10)
364 #define ID_DIN (1<<9)
365 #define ID_CLOCK (1<<8)
366 #define QUICK_RD_RETRY (1<<7)
367 #define QUICK_WR_RETRY (1<<6)
368 #define OUTFF_ENB (1<<5)
369 #define CMDFF_ENB (1<<4)
370 #define PERR_INT_ENB (1<<2)
371 #define IGNORE_INTR (1<<0)
374 #define SWAP_RNUM_MAX(x) (x<<27) argument
375 #define DATA_WR_SWAP (1<<20)
376 #define DESC_RD_SWAP (1<<19)
377 #define DATA_RD_SWAP (1<<18)
378 #define INTR_SWAP (1<<17)
379 #define DESC_WR_SWAP (1<<16)
380 #define SDRAM_INIT (1<<15)
381 #define BIG_ENDIAN_HOST (1<<14)
382 #define XFER_SIZE (1<<7)
388 #define LB_MEM_HNDSHK (1<<30)
393 #define LB_64_ENB (1<<3)
394 #define LB_TWR (1<<2)
395 #define LB_TRP (1<<1)
396 #define LB_TRAS (1<<0)
399 #define INT_MASK_D (1<<15)
400 #define INT_MASK_C (1<<14)
401 #define INT_MASK_B (1<<13)
402 #define INT_MASK_A (1<<12)
403 #define INT_CLEAR_D (1<<11)
404 #define INT_CLEAR_C (1<<10)
405 #define INT_CLEAR_B (1<<9)
406 #define INT_CLEAR_A (1<<8)
411 #define IRQ_BASE(x) (x<<12) argument
412 #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */
413 #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK) argument
415 #define IRQ_SIZE(x) (x<<22) argument
416 #define IRQ_THRESH(x) (x<<12) argument
417 #define IRQ_HEAD(x) (x<<2) argument
418 /* #define IRQ_PENDING (1) conflict with linux/irq.h */
420 #define IRQ_ADDRSEL(x) (x<<2) argument
422 #define IRQ_INT_B (1<<2)
451 #define RBP_TAIL(x) ((x)<<3) argument
452 #define RBP_MASK(x) ((x)|0x1fff) argument
454 #define RBP_QSIZE(x) ((x)<<14) argument
455 #define RBP_INT_ENB (1<<13)
456 #define RBP_THRESH(x) (x) argument
530 #define RBRQ_THRESH(x) ((x)<<13) argument
531 #define RBRQ_SIZE(x) (x) argument
533 #define RBRQ_TIME(x) ((x)<<8) argument
534 #define RBRQ_COUNT(x) (x) argument
536 /* fill in 1 ... 7 later */
542 #define TBRQ_THRESH(x) (x) argument
544 /* fill in 1 ... 7 later */
547 #define PHY_INT_ENB (1<<10)
548 #define OAM_GID(x) (x<<7) argument
549 #define PTMR_PRE(x) (x) argument
589 #define SLICE_X(x) (x<<28) argument
590 #define ARB_RNUM_MAX(x) (x<<23) argument
591 #define TH_PRTY(x) (x<<21) argument
592 #define RH_PRTY(x) (x<<19) argument
593 #define TL_PRTY(x) (x<<17) argument
594 #define RL_PRTY(x) (x<<15) argument
595 #define BUS_MULTI(x) (x<<8) argument
596 #define NET_PREF(x) (x) argument
599 #define BANK_ON (1<<14)
600 #define WIDE_DATA (1<<13)
601 #define TWR_WAIT (1<<12)
602 #define TRP_WAIT (1<<11)
603 #define TRAS_WAIT (1<<10)
604 #define REF_RATE(x) (x) argument
609 #define RCC_BUSY (1)
612 #define TM_DESL2 (1<<10)
613 #define TM_BANK_WAIT(x) (x<<6) argument
614 #define TM_ADD_BANK4(x) (x<<4) argument
615 #define TM_PAR_CHECK(x) (x<<3) argument
616 #define TM_RW_WAIT(x) (x<<2) argument
617 #define TM_SRAM_TYPE(x) (x) argument
626 #define DRF_THRESH(x) (x<<22) argument
627 #define TX_UT_MODE(x) (x<<21) argument
628 #define TX_VCI_MASK(x) (x<<17) argument
629 #define LBFREE_CNT(x) (x) argument
632 #define CPCS_UU(x) (x<<8) argument
633 #define CPI(x) (x) argument
636 #define RM_DESL2(x) (x<<10) argument
637 #define RM_BANK_WAIT(x) (x<<6) argument
638 #define RM_ADD_BANK(x) (x<<4) argument
639 #define RM_PAR_CHECK(x) (x<<3) argument
640 #define RM_RW_WAIT(x) (x<<2) argument
641 #define RM_SRAM_TYPE(x) (x) argument
648 #define UT_RD_DELAY(x) (x<<11) argument
649 #define WRAP_MODE(x) (x<<10) argument
650 #define RC_UT_MODE(x) (x<<9) argument
651 #define RX_ENABLE (1<<8)
652 #define RX_VALVP(x) (x<<4) argument
653 #define RX_VALVC(x) (x) argument
663 #define LB_SIZE(x) (x) argument
668 #define CON_CTL_TCM (1<<30)
670 #define CON_CTL_WRITE (1<<29)
672 #define CON_CTL_BUSY (1<<28)
673 #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */
674 #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */
675 #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */
676 #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */
677 #define CON_CTL_ADDR(x) (x) argument
701 #define TX_ENABLE (1<<28)
702 #define ER_ENABLE (1<<27)
738 #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */
743 #define TSR0_CONN_STATE(x) ((x>>28) & 0x7) argument
744 #define TSR0_USE_WMIN (1<<23)
745 #define TSR0_GROUP(x) ((x & 0x7)<<18) argument
747 #define TSR0_UBR (1<<16)
749 #define TSR0_PROT (1<<15)
751 #define TSR0_AAL0 (1<<12)
753 #define TSR0_HALT_ER (1<<11)
754 #define TSR0_MARK_CI (1<<10)
755 #define TSR0_MARK_ER (1<<9)
756 #define TSR0_UPDATE_GER (1<<8)
757 #define TSR0_RC_INDEX(x) (x & 0x1F) argument
759 #define TSR1_PCR(x) ((x & 0x7FFF)<<16) argument
760 #define TSR1_MCR(x) (x & 0x7FFF) argument
762 #define TSR2_ACR(x) ((x & 0x7FFF)<<16) argument
764 #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24) argument
765 #define TSR3_CRM_CNT(x) (x & 0xFFFF) argument
767 #define TSR4_FLUSH_CONN (1<<31)
768 #define TSR4_SESSION_ENDED (1<<30)
769 #define TSR4_CRC10 (1<<28)
770 #define TSR4_NULL_CRC10 (1<<27)
771 #define TSR4_PROT (1<<26)
773 #define TSR4_AAL0 (1<<23)
776 #define TSR9_OPEN_CONN (1<<20)
778 #define TSR11_ICR(x) ((x & 0x7FFF)<<16) argument
779 #define TSR11_TRM(x) ((x & 0x7)<<13) argument
780 #define TSR11_NRM(x) ((x & 0x7)<<10) argument
781 #define TSR11_ADTF(x) (x & 0x3FF) argument
783 #define TSR13_RDF(x) ((x & 0xF)<<23) argument
784 #define TSR13_RIF(x) ((x & 0xF)<<19) argument
785 #define TSR13_CDF(x) ((x & 0x7)<<16) argument
786 #define TSR13_CRM(x) (x & 0xFFFF) argument
788 #define TSR14_DELETE (1<<31)
789 #define TSR14_ABR_CLOSE (1<<16)
791 /* 2.7.1 per connection receieve state registers */
793 #define RSR0_START_PDU (1<<10)
794 #define RSR0_OPEN_CONN (1<<6)
796 #define RSR0_PPD_ENABLE (1<<5)
797 #define RSR0_EPD_ENABLE (1<<4)
798 #define RSR0_TCP_CKSUM (1<<3)
800 #define RSR0_AAL0 (1)
805 #define RSR1_AQI_ENABLE (1<<20)
806 #define RSR1_RBPL_ONLY (1<<19)
807 #define RSR1_GROUP(x) ((x)<<16) argument
809 #define RSR4_AQI_ENABLE (1<<30)
810 #define RSR4_GROUP(x) ((x)<<27) argument
811 #define RSR4_RBPL_ONLY (1<<26)
819 #define TPD_CELLTYPE(x) (x<<3) argument
820 #define TPD_EOS (1<<2)
821 #define TPD_CLP (1<<1)
822 #define TPD_INT (1<<0)
823 #define TPD_LST (1<<31)