Lines Matching refs:he_writel
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0) macro
185 he_writel(he_dev, val, CON_DAT); in he_writel_internal()
187 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL); in he_writel_internal()
203 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL); in he_readl_internal()
455 he_writel(he_dev, lbufd_index, RLBF0_H); in he_init_rx_lbfp0()
471 he_writel(he_dev, lbufd_index - 2, RLBF0_T); in he_init_rx_lbfp0()
472 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C); in he_init_rx_lbfp0()
485 he_writel(he_dev, lbufd_index, RLBF1_H); in he_init_rx_lbfp1()
501 he_writel(he_dev, lbufd_index - 2, RLBF1_T); in he_init_rx_lbfp1()
502 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C); in he_init_rx_lbfp1()
515 he_writel(he_dev, lbufd_index, TLBF_H); in he_init_tx_lbfp()
531 he_writel(he_dev, lbufd_index - 1, TLBF_T); in he_init_tx_lbfp()
548 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H); in he_init_tpdrq()
549 he_writel(he_dev, 0, TPDRQ_T); in he_init_tpdrq()
550 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S); in he_init_tpdrq()
776 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_init_group()
777 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_init_group()
778 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_init_group()
779 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_init_group()
832 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32)); in he_init_group()
833 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), in he_init_group()
835 he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4, in he_init_group()
837 he_writel(he_dev, in he_init_group()
854 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16)); in he_init_group()
855 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16)); in he_init_group()
856 he_writel(he_dev, in he_init_group()
861 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7), in he_init_group()
864 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1), in he_init_group()
879 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16)); in he_init_group()
880 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16)); in he_init_group()
881 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16)); in he_init_group()
882 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16)); in he_init_group()
930 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE); in he_init_irq()
931 he_writel(he_dev, in he_init_irq()
934 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL); in he_init_irq()
935 he_writel(he_dev, 0x0, IRQ0_DATA); in he_init_irq()
937 he_writel(he_dev, 0x0, IRQ1_BASE); in he_init_irq()
938 he_writel(he_dev, 0x0, IRQ1_HEAD); in he_init_irq()
939 he_writel(he_dev, 0x0, IRQ1_CNTL); in he_init_irq()
940 he_writel(he_dev, 0x0, IRQ1_DATA); in he_init_irq()
942 he_writel(he_dev, 0x0, IRQ2_BASE); in he_init_irq()
943 he_writel(he_dev, 0x0, IRQ2_HEAD); in he_init_irq()
944 he_writel(he_dev, 0x0, IRQ2_CNTL); in he_init_irq()
945 he_writel(he_dev, 0x0, IRQ2_DATA); in he_init_irq()
947 he_writel(he_dev, 0x0, IRQ3_BASE); in he_init_irq()
948 he_writel(he_dev, 0x0, IRQ3_HEAD); in he_init_irq()
949 he_writel(he_dev, 0x0, IRQ3_CNTL); in he_init_irq()
950 he_writel(he_dev, 0x0, IRQ3_DATA); in he_init_irq()
954 he_writel(he_dev, 0x0, GRP_10_MAP); in he_init_irq()
955 he_writel(he_dev, 0x0, GRP_32_MAP); in he_init_irq()
956 he_writel(he_dev, 0x0, GRP_54_MAP); in he_init_irq()
957 he_writel(he_dev, 0x0, GRP_76_MAP); in he_init_irq()
1054 he_writel(he_dev, 0x0, RESET_CNTL); in he_start()
1055 he_writel(he_dev, 0xff, RESET_CNTL); in he_start()
1107 he_writel(he_dev, lb_swap, LB_SWAP); in he_start()
1110 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL); in he_start()
1114 he_writel(he_dev, lb_swap, LB_SWAP); in he_start()
1123 he_writel(he_dev, host_cntl, HOST_CNTL); in he_start()
1221 he_writel(he_dev, in he_start()
1228 he_writel(he_dev, BANK_ON | in he_start()
1232 he_writel(he_dev, in he_start()
1235 he_writel(he_dev, in he_start()
1239 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG); in he_start()
1241 he_writel(he_dev, in he_start()
1247 he_writel(he_dev, DRF_THRESH(0x20) | in he_start()
1252 he_writel(he_dev, 0x0, TXAAL5_PROTO); in he_start()
1254 he_writel(he_dev, PHY_INT_ENB | in he_start()
1297 he_writel(he_dev, CONFIG_TSRB, TSRB_BA); in he_start()
1298 he_writel(he_dev, CONFIG_TSRC, TSRC_BA); in he_start()
1299 he_writel(he_dev, CONFIG_TSRD, TSRD_BA); in he_start()
1300 he_writel(he_dev, CONFIG_TMABR, TMABR_BA); in he_start()
1301 he_writel(he_dev, CONFIG_TPDBA, TPD_BA); in he_start()
1331 he_writel(he_dev, 0x08000, RCMLBM_BA); in he_start()
1332 he_writel(he_dev, 0x0e000, RCMRSRB_BA); in he_start()
1333 he_writel(he_dev, 0x0d800, RCMABR_BA); in he_start()
1340 he_writel(he_dev, 0x0, RLBC_H); in he_start()
1341 he_writel(he_dev, 0x0, RLBC_T); in he_start()
1342 he_writel(he_dev, 0x0, RLBC_H2); in he_start()
1344 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */ in he_start()
1345 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */ in he_start()
1349 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA); in he_start()
1354 he_writel(he_dev, 0x000f, G0_INMQ_S); in he_start()
1355 he_writel(he_dev, 0x200f, G0_INMQ_L); in he_start()
1357 he_writel(he_dev, 0x001f, G1_INMQ_S); in he_start()
1358 he_writel(he_dev, 0x201f, G1_INMQ_L); in he_start()
1360 he_writel(he_dev, 0x002f, G2_INMQ_S); in he_start()
1361 he_writel(he_dev, 0x202f, G2_INMQ_L); in he_start()
1363 he_writel(he_dev, 0x003f, G3_INMQ_S); in he_start()
1364 he_writel(he_dev, 0x203f, G3_INMQ_L); in he_start()
1366 he_writel(he_dev, 0x004f, G4_INMQ_S); in he_start()
1367 he_writel(he_dev, 0x204f, G4_INMQ_L); in he_start()
1369 he_writel(he_dev, 0x005f, G5_INMQ_S); in he_start()
1370 he_writel(he_dev, 0x205f, G5_INMQ_L); in he_start()
1372 he_writel(he_dev, 0x006f, G6_INMQ_S); in he_start()
1373 he_writel(he_dev, 0x206f, G6_INMQ_L); in he_start()
1375 he_writel(he_dev, 0x007f, G7_INMQ_S); in he_start()
1376 he_writel(he_dev, 0x207f, G7_INMQ_L); in he_start()
1378 he_writel(he_dev, 0x0000, G0_INMQ_S); in he_start()
1379 he_writel(he_dev, 0x0008, G0_INMQ_L); in he_start()
1381 he_writel(he_dev, 0x0001, G1_INMQ_S); in he_start()
1382 he_writel(he_dev, 0x0009, G1_INMQ_L); in he_start()
1384 he_writel(he_dev, 0x0002, G2_INMQ_S); in he_start()
1385 he_writel(he_dev, 0x000a, G2_INMQ_L); in he_start()
1387 he_writel(he_dev, 0x0003, G3_INMQ_S); in he_start()
1388 he_writel(he_dev, 0x000b, G3_INMQ_L); in he_start()
1390 he_writel(he_dev, 0x0004, G4_INMQ_S); in he_start()
1391 he_writel(he_dev, 0x000c, G4_INMQ_L); in he_start()
1393 he_writel(he_dev, 0x0005, G5_INMQ_S); in he_start()
1394 he_writel(he_dev, 0x000d, G5_INMQ_L); in he_start()
1396 he_writel(he_dev, 0x0006, G6_INMQ_S); in he_start()
1397 he_writel(he_dev, 0x000e, G6_INMQ_L); in he_start()
1399 he_writel(he_dev, 0x0007, G7_INMQ_S); in he_start()
1400 he_writel(he_dev, 0x000f, G7_INMQ_L); in he_start()
1405 he_writel(he_dev, 0x0, MCC); in he_start()
1406 he_writel(he_dev, 0x0, OEC); in he_start()
1407 he_writel(he_dev, 0x0, DCC); in he_start()
1408 he_writel(he_dev, 0x0, CEC); in he_start()
1436 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_start()
1437 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_start()
1438 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_start()
1439 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1442 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32)); in he_start()
1443 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32)); in he_start()
1444 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1446 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32)); in he_start()
1448 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16)); in he_start()
1449 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16)); in he_start()
1450 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0), in he_start()
1452 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16)); in he_start()
1454 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16)); in he_start()
1455 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16)); in he_start()
1456 he_writel(he_dev, TBRQ_THRESH(0x1), in he_start()
1458 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16)); in he_start()
1470 he_writel(he_dev, he_dev->hsp_phys, HSP_BA); in he_start()
1499 he_writel(he_dev, reg, RC_CONFIG); in he_start()
1550 he_writel(he_dev, reg, RC_CONFIG); in he_stop()
1791 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head), in he_service_rbrq()
1872 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head), in he_service_tbrq()
1921 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T); in he_service_rbpl()
2002 he_writel(he_dev, in he_tasklet()
2041 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */ in he_irq_handler()
2110 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T); in __enqueue_tpd()
2678 he_writel(he_dev, val, FRAMER + (addr*4)); in he_phy_put()
2795 he_writel(he_dev, val, HOST_CNTL); in read_prom_byte()
2799 he_writel(he_dev, val | readtab[i], HOST_CNTL); in read_prom_byte()
2805 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); in read_prom_byte()
2807 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); in read_prom_byte()
2814 he_writel(he_dev, val, HOST_CNTL); in read_prom_byte()
2818 he_writel(he_dev, val | clocktab[j++], HOST_CNTL); in read_prom_byte()
2823 he_writel(he_dev, val | clocktab[j++], HOST_CNTL); in read_prom_byte()
2827 he_writel(he_dev, val | ID_CS, HOST_CNTL); in read_prom_byte()