Lines Matching refs:eni_in
154 #define eni_in(r) readl(eni_dev->reg+(r)*4) macro
316 eni_out(eni_in(MID_MC_S) & in rx_ident_err()
452 dma_wr = eni_in(MID_DMA_WR_RX); in do_rx_dma()
453 dma_rd = eni_in(MID_DMA_RD_RX); in do_rx_dma()
684 while (eni_in(MID_SERV_WRITE) != eni_dev->serv_read) { in get_service()
916 eni_dev->serv_read = eni_in(MID_SERV_WRITE); in start_rx()
1088 eni_in(MID_TX_RDPTR(tx->index)),tx->words)) { in do_tx()
1094 dma_wr = eni_in(MID_DMA_WR_TX); in do_tx()
1095 dma_rd = eni_in(MID_DMA_RD_TX); in do_tx()
1222 (unsigned) eni_in(MID_TX_DESCRSTART(tx->index))); in dequeue_tx()
1224 eni_in(MID_TX_DESCRSTART(tx->index))) { in dequeue_tx()
1337 tx->tx_pos = eni_in(MID_TX_DESCRSTART(tx->index)) & in reserve_or_set_tx()
1422 while (eni_in(MID_TX_RDPTR(eni_vcc->tx->index)) != in close_tx()
1423 eni_in(MID_TX_DESCRSTART(eni_vcc->tx->index))) in close_tx()
1499 reason = eni_in(MID_ISA); in eni_int()
1509 eni_dev->lost += eni_in(MID_STAT) & MID_OVFL_TRASH; in eni_int()
1767 if (!(eni_in(MID_RES_ID_MCON) & 0x200) != !eni_dev->asic) { in eni_do_init()
1770 dev->number,(unsigned) eni_in(MID_RES_ID_MCON)); in eni_do_init()
1781 eni_in(MID_RES_ID_MCON) & 0x200 ? "ASIC" : "FPGA", in eni_do_init()
1782 media_name[eni_in(MID_RES_ID_MCON) & DAUGHTER_ID]); in eni_do_init()
1876 eni_out(eni_in(MID_MC_S) | (1 << MID_INT_SEL_SHIFT) | in eni_start()
1880 (void) eni_in(MID_ISA); /* clear Midway interrupts */ in eni_start()