36 	VSC_MMIO_BAR			= 0,
39 	VSC_SATA_INT_STAT_OFFSET	= 0x00,
40 	VSC_SATA_INT_MASK_OFFSET	= 0x04,
43 	VSC_SATA_TF_CMD_OFFSET		= 0x00,
44 	VSC_SATA_TF_DATA_OFFSET		= 0x00,
45 	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
46 	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
47 	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
48 	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
49 	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
50 	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
51 	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
52 	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
53 	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
54 	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
55 	VSC_SATA_TF_CTL_OFFSET		= 0x29,
58 	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
59 	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
60 	VSC_SATA_DMA_CMD_OFFSET		= 0x70,
63 	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
64 	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
65 	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,
68 	VSC_SATA_PORT_OFFSET		= 0x200,
71 	VSC_SATA_INT_ERROR_CRC		= 0x40,
72 	VSC_SATA_INT_ERROR_T		= 0x20,
73 	VSC_SATA_INT_ERROR_P		= 0x10,
74 	VSC_SATA_INT_ERROR_R		= 0x8,
75 	VSC_SATA_INT_ERROR_E		= 0x4,
76 	VSC_SATA_INT_ERROR_M		= 0x2,
77 	VSC_SATA_INT_PHY_CHANGE		= 0x1,
90 	return 0;  in vsc_sata_scr_read()
100 	return 0;  in vsc_sata_scr_write()
111 	writeb(0, mask_addr);  in vsc_freeze()
122 	writeb(0xff, mask_addr);  in vsc_thaw()
135 		mask |= 0x80;  in vsc_intr_mask_update()
137 		mask &= 0x7F;  in vsc_intr_mask_update()
222 	int handled = 0;  in vsc_port_intr()
252 	unsigned int handled = 0;  in vsc_sata_interrupt()
257 	if (unlikely(status == 0xffffffff || status == 0)) {  in vsc_sata_interrupt()
260 				": IRQ status == 0xffffffff, PCI fault or device removal?\n");  in vsc_sata_interrupt()
266 	for (i = 0; i < host->n_ports; i++) {  in vsc_sata_interrupt()
267 		u8 port_status = (status >> (8 * i)) & 0xff;  in vsc_sata_interrupt()
315 	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);  in vsc_sata_setup_port()
316 	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);  in vsc_sata_setup_port()
348 	if (pci_resource_len(pdev, 0) == 0)  in vsc_sata_init_one()
361 	for (i = 0; i < host->n_ports; i++) {  in vsc_sata_init_one()
383 	if (cls == 0x00)  in vsc_sata_init_one()
384 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);  in vsc_sata_init_one()
386 	if (pci_enable_msi(pdev) == 0)  in vsc_sata_init_one()
387 		pci_intx(pdev, 0);  in vsc_sata_init_one()
390 	 * Config offset 0x98 is "Extended Control and Status Register 0"  in vsc_sata_init_one()
392 	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.  in vsc_sata_init_one()
395 	pci_write_config_dword(pdev, 0x98, 0);  in vsc_sata_init_one()
403 	{ PCI_VENDOR_ID_VITESSE, 0x7174,
404 	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
405 	{ PCI_VENDOR_ID_INTEL, 0x3200,
406 	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },