47 	SIL24_HOST_BAR		= 0,
69 	HOST_SLOT_STAT		= 0x00, /* 32 bit slot stat * 4 */
70 	HOST_CTRL		= 0x40,
71 	HOST_IRQ_STAT		= 0x44,
72 	HOST_PHY_CFG		= 0x48,
73 	HOST_BIST_CTRL		= 0x50,
74 	HOST_BIST_PTRN		= 0x54,
75 	HOST_BIST_STAT		= 0x58,
76 	HOST_MEM_BIST_STAT	= 0x5c,
77 	HOST_FLASH_CMD		= 0x70,
79 	HOST_FLASH_DATA		= 0x74,
80 	HOST_TRANSITION_DETECT	= 0x75,
81 	HOST_GPIO_CTRL		= 0x76,
82 	HOST_I2C_ADDR		= 0x78, /* 32 bit */
83 	HOST_I2C_DATA		= 0x7c,
84 	HOST_I2C_XFER_CNT	= 0x7e,
85 	HOST_I2C_CTRL		= 0x7f,
100 	 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 	PORT_REGS_SIZE		= 0x2000,
104 	PORT_LRAM		= 0x0000, /* 31 LRAM slots and PMP regs */
105 	PORT_LRAM_SLOT_SZ	= 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
107 	PORT_PMP		= 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
108 	PORT_PMP_STATUS		= 0x0000, /* port device status offset */
109 	PORT_PMP_QACTIVE	= 0x0004, /* port device QActive offset */
110 	PORT_PMP_SIZE		= 0x0008, /* 8 bytes per PMP */
113 	PORT_CTRL_STAT		= 0x1000, /* write: ctrl-set, read: stat */
114 	PORT_CTRL_CLR		= 0x1004, /* write: ctrl-clear */
115 	PORT_IRQ_STAT		= 0x1008, /* high: status, low: interrupt */
116 	PORT_IRQ_ENABLE_SET	= 0x1010, /* write: enable-set */
117 	PORT_IRQ_ENABLE_CLR	= 0x1014, /* write: enable-clear */
118 	PORT_ACTIVATE_UPPER_ADDR= 0x101c,
119 	PORT_EXEC_FIFO		= 0x1020, /* command execution fifo */
120 	PORT_CMD_ERR		= 0x1024, /* command error number */
121 	PORT_FIS_CFG		= 0x1028,
122 	PORT_FIFO_THRES		= 0x102c,
124 	PORT_DECODE_ERR_CNT	= 0x1040,
125 	PORT_DECODE_ERR_THRESH	= 0x1042,
126 	PORT_CRC_ERR_CNT	= 0x1044,
127 	PORT_CRC_ERR_THRESH	= 0x1046,
128 	PORT_HSHK_ERR_CNT	= 0x1048,
129 	PORT_HSHK_ERR_THRESH	= 0x104a,
131 	PORT_PHY_CFG		= 0x1050,
132 	PORT_SLOT_STAT		= 0x1800,
133 	PORT_CMD_ACTIVATE	= 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
134 	PORT_CONTEXT		= 0x1e04,
135 	PORT_EXEC_DIAG		= 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
136 	PORT_PSD_DIAG		= 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
137 	PORT_SCONTROL		= 0x1f00,
138 	PORT_SSTATUS		= 0x1f04,
139 	PORT_SERROR		= 0x1f08,
140 	PORT_SACTIVE		= 0x1f0c,
143 	PORT_CS_PORT_RST	= (1 << 0), /* port reset */
147 	PORT_CS_CDB16		= (1 << 5), /* 0=12b cdb, 1=16b cdb */
154 	/* bits[11:0] are masked */
155 	PORT_IRQ_COMPLETE	= (1 << 0), /* command(s) completed */
174 	PORT_IRQ_MASKED_MASK	= 0x7ff,
175 	PORT_IRQ_RAW_MASK	= (0x7ff << PORT_IRQ_RAW_SHIFT),
206 	PRB_CTRL_PROTOCOL	= (1 << 0), /* override def. ATA protocol */
213 	PRB_PROT_PACKET		= (1 << 0),
232 	BID_SIL3124		= 0,
242 	IRQ_STAT_4PORTS		= 0xf,
265 	[0]			= { AC_ERR_DEV, 0,
267 	[PORT_CERR_DEV]		= { AC_ERR_DEV, 0,
269 	[PORT_CERR_SDB]		= { AC_ERR_DEV, 0,
316  * The preview driver always returned 0 for status.  We emulate it
354 	{ PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
355 	{ PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
356 	{ PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
357 	{ PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
358 	{ PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
359 	{ PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
360 	{ PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
424 #define SIL24_NPORTS2FLAG(nports)	((((unsigned)(nports) - 1) & 0x3) << 30)
425 #define SIL24_FLAG2NPORTS(flag)		((((flag) >> 30) & 0x3) + 1)
458 		return 0;  in sil24_tag()
494 	[SCR_CONTROL]	= 0,
506 		return 0;  in sil24_scr_read()
517 		return 0;  in sil24_scr_write()
533 	writew(0x8000, port + PORT_DECODE_ERR_THRESH);  in sil24_config_port()
534 	writew(0x8000, port + PORT_CRC_ERR_THRESH);  in sil24_config_port()
535 	writew(0x8000, port + PORT_HSHK_ERR_THRESH);  in sil24_config_port()
536 	writew(0x0000, port + PORT_DECODE_ERR_CNT);  in sil24_config_port()
537 	writew(0x0000, port + PORT_CRC_ERR_CNT);  in sil24_config_port()
538 	writew(0x0000, port + PORT_HSHK_ERR_CNT);  in sil24_config_port()
564 	for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {  in sil24_clear_pmp()
567 		writel(0, pmp_base + PORT_PMP_STATUS);  in sil24_clear_pmp()
568 		writel(0, pmp_base + PORT_PMP_QACTIVE);  in sil24_clear_pmp()
586 				PORT_CS_RDY, 0, 10, 100);  in sil24_init_port()
594 	return 0;  in sil24_init_port()
604 	struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;  in sil24_exec_polled_cmd()
625 	irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,  in sil24_exec_polled_cmd()
632 		rc = 0;  in sil24_exec_polled_cmd()
654 	unsigned int timeout_msec = 0;  in sil24_softreset()
670 	rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,  in sil24_softreset()
680 	sil24_read_tf(ap, 0, &tf);  in sil24_softreset()
683 	return 0;  in sil24_softreset()
696 	int did_port_rst = 0;  in sil24_hardreset()
712 		ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,  in sil24_hardreset()
719 		pp->do_port_rst = 0;  in sil24_hardreset()
746 			return 0;  in sil24_hardreset()
779 		sge->flags = 0;  in sil24_fill_sg()
840 	u16 ctrl = 0;  in sil24_qc_prep()
848 			u16 prot = 0;  in sil24_qc_prep()
861 		memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));  in sil24_qc_prep()
901 	return 0;  in sil24_qc_issue()
916 	if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&  in sil24_pmp_attach()
917 	    sata_pmp_gscr_devid(gscr) == 0x4140) {  in sil24_pmp_attach()
927 	sil24_config_pmp(ap, 0);  in sil24_pmp_detach()
953 	writel(0xffff, port + PORT_IRQ_ENABLE_CLR);  in sil24_freeze()
976 	int abort = 0, freeze = 0;  in sil24_error_intr()
988 	ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);  in sil24_error_intr()
1013 		unsigned int err_mask = 0, action = 0;  in sil24_error_intr()
1035 			pmp = (context >> 5) & 0xf;  in sil24_error_intr()
1043 				ata_ehi_push_desc(ehi, "irq_stat 0x%08x",  in sil24_error_intr()
1121 	if (rc > 0)  in sil24_host_intr()
1123 	if (rc < 0) {  in sil24_host_intr()
1134 			"spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",  in sil24_host_intr()
1142 	unsigned handled = 0;  in sil24_interrupt()
1148 	if (status == 0xffffffff) {  in sil24_interrupt()
1149 		dev_err(host->dev, "IRQ status == 0xffffffff, "  in sil24_interrupt()
1159 	for (i = 0; i < host->n_ports; i++)  in sil24_interrupt()
1179 	pp->do_port_rst = 0;  in sil24_error_handler()
1215 	return 0;  in sil24_port_start()
1225 	writel(0, host_base + HOST_FLASH_CMD);  in sil24_init_controller()
1228 	writel(0, host_base + HOST_CTRL);  in sil24_init_controller()
1231 	for (i = 0; i < host->n_ports; i++) {  in sil24_init_controller()
1237 		writel(0x20c, port + PORT_PHY_CFG);  in sil24_init_controller()
1299 				    SIL24_FLAG2NPORTS(ppi[0]->flags));  in sil24_init_one()
1320 		pci_intx(pdev, 0);  in sil24_init_one()
1346 	return 0;  in sil24_pci_device_resume()
1354 	return 0;  in sil24_port_resume()