192 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_freeze()  local
194 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_freeze()
200 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_thaw()  local
203 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */  in qs_thaw()
354 	u8 __iomem *mmio_base = qs_mmio_base(host);  in qs_intr_pkt()  local
357 		u32 sff0 = readl(mmio_base + QS_HST_SFF);  in qs_intr_pkt()
358 		u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);  in qs_intr_pkt()
460 	void __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_port_start()  local
461 	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);  in qs_port_start()
482 	void __iomem *mmio_base = qs_mmio_base(host);  in qs_host_stop()  local
484 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_stop()
485 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_stop()
490 	void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];  in qs_host_init()  local
493 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_init()
494 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_init()
498 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
503 	writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */  in qs_host_init()
506 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
515 	writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */  in qs_host_init()
528 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)  in qs_set_dma_masks()  argument
530 	u32 bus_info = readl(mmio_base + QS_HID_HPHY);  in qs_set_dma_masks()