829 static inline void writelfl(unsigned long data, void __iomem *addr)  in writelfl()  function
953 				writelfl(new, addr); /* read after write */  in mv_write_cached_reg()
975 	writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,  in mv_set_edma_ptrs()
977 	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);  in mv_set_edma_ptrs()
987 	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);  in mv_set_edma_ptrs()
988 	writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,  in mv_set_edma_ptrs()
1006 	writelfl(mask, hpriv->main_irq_mask_addr);  in mv_write_main_irq_mask()
1047 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1051 	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1055 		writelfl(0, port_mmio + FIS_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1150 		writelfl(EDMA_EN, port_mmio + EDMA_CMD);  in mv_start_edma()
1190 	writelfl(EDMA_DS, port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1361 				writelfl(lp_phy_val, lp_phy_addr);  in mv_scr_write()
1364 		writelfl(val, addr);  in mv_scr_write()
1627 	writelfl(cfg, port_mmio + EDMA_CFG);  in mv_edma_cfg()
1860 	writelfl(pp->sg_tbl_dma[qc->hw_tag],  in mv_bmdma_setup()
1882 	writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_start()
1903 		writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
2202 	writelfl(ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2209 	writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);  in mv_send_fis()
2210 	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2221 	writelfl(old_ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2323 		writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,  in mv_qc_issue()
2625 		writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2627 	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2801 		writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |  in mv_process_crpb_entries()
2901 			writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);  in mv_host_intr()
2930 	writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3043 		writelfl(val, addr + ofs);  in mv5_scr_write()
3524 	writelfl(ifcfg, port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3538 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3549 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3551 	writelfl(0, port_mmio + EDMA_CMD);  in mv_reset_channel()
3568 			writelfl(reg, port_mmio + SATA_IFCTL);  in mv_pmp_select()
3647 	writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);  in mv_eh_thaw()
3685 	writelfl(readl(serr), serr);  in mv_port_init()
3686 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_port_init()
3689 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);  in mv_port_init()
3728 		writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);  in mv_60x1b2_errata_pci7()
3940 		writelfl(0, hc_mmio + HC_IRQ_CAUSE);  in mv_init_host()
3945 		writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_init_host()
3948 		writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);  in mv_init_host()