62 static struct phy_lane_info port_data[CPHY_PORT_COUNT];  variable
217 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_read()
219 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_read()
220 	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_read()
227 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_write()
229 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_write()
230 	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_write()
259 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_disable_overrides()
261 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_disable_overrides()
270 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_tx_attenuation()
289 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_rx_mode()
313 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_override_lane()
316 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_override_lane()
323 	cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);  in highbank_cphy_override_lane()
334 	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);  in highbank_initialize_phys()
355 		port_data[port].lane_mapping = phy_data.args[0];  in highbank_initialize_phys()
357 		port_data[port].phy_devs = tmp;  in highbank_initialize_phys()
358 		port_data[port].phy_base = cphy_base[phy];  in highbank_initialize_phys()
365 		port_data[i].tx_atten = (u8) tx_atten[i];  in highbank_initialize_phys()