45 	int control = 0;  in radisys_set_piomode()
50 	 *	timing port at 0x44. The Radisys is a relative of the PIIX  in radisys_set_piomode()
55 	u8 timings[][2]	= { { 0, 0 },	/* Check me */  in radisys_set_piomode()
56 			    { 0, 0 },  in radisys_set_piomode()
61 	if (pio > 0)  in radisys_set_piomode()
66 	pci_read_config_word(dev, 0x40, &idetm_data);  in radisys_set_piomode()
70 	idetm_data &= 0xCCCC;  in radisys_set_piomode()
72 	idetm_data |= (timings[pio][0] << 12) |  in radisys_set_piomode()
74 	pci_write_config_word(dev, 0x40, idetm_data);  in radisys_set_piomode()
98 	u8 timings[][2]	= { { 0, 0 },  in radisys_set_dmamode()
99 			    { 0, 0 },  in radisys_set_dmamode()
109 	pci_read_config_word(dev, 0x40, &idetm_data);  in radisys_set_dmamode()
110 	pci_read_config_byte(dev, 0x48, &udma_enable);  in radisys_set_dmamode()
129 		idetm_data &= 0xCCCC;  in radisys_set_dmamode()
131 		idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);  in radisys_set_dmamode()
137 		/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */  in radisys_set_dmamode()
139 		pci_read_config_byte(dev, 0x4A, &udma_mode);  in radisys_set_dmamode()
146 		pci_write_config_byte(dev, 0x4A, udma_mode);  in radisys_set_dmamode()
150 	pci_write_config_word(dev, 0x40, idetm_data);  in radisys_set_dmamode()
151 	pci_write_config_byte(dev, 0x48, udma_enable);  in radisys_set_dmamode()
227 	return ata_pci_bmdma_init_one(pdev, ppi, &radisys_sht, NULL, 0);  in radisys_init_one()
231 	{ PCI_VDEVICE(RADISYS, 0x8201), },