23 #define cec4		w2(0xc);w2(0xe);w2(0xe);w2(0xc);w2(4);w2(4);w2(4);
24 #define j44(l,h)	(((l>>4)&0x0f)|(h&0xf0))
27  * cont = 0 - access the IDE register file
30 static int  cont_map[2] = { 0x08, 0x10 };
62 	case 0:  in frpw_read_block_int()
64 		for (k = 0; k < count; k++) {  in frpw_read_block_int()
74 		w2(4); w0(regr + 0xc0); cec4;  in frpw_read_block_int()
75 		w0(0xff);  in frpw_read_block_int()
76 		for (k = 0; k < count; k++) {  in frpw_read_block_int()
77 			w2(0xa4 + ph);  in frpw_read_block_int()
81 		w2(0xac); w2(0xa4); w2(4);  in frpw_read_block_int()
85 		w2(4); w0(regr + 0x80); cec4;  in frpw_read_block_int()
86 		for (k = 0; k < count; k++)  in frpw_read_block_int()
88 		w2(0xac); w2(0xa4);  in frpw_read_block_int()
93 		w2(4); w0(regr + 0x80); cec4;  in frpw_read_block_int()
94 		for (k = 0; k < count - 2; k++)  in frpw_read_block_int()
96 		w2(0xac); w2(0xa4);  in frpw_read_block_int()
103 		w2(4); w0(regr + 0x80); cec4;  in frpw_read_block_int()
104 		for (k = 0; k < count / 2 - 1; k++)  in frpw_read_block_int()
106 		w2(0xac); w2(0xa4);  in frpw_read_block_int()
113 		w2(4); w0(regr + 0x80); cec4;  in frpw_read_block_int()
114 		for (k = 0; k < count / 4 - 1; k++)  in frpw_read_block_int()
118 		w2(0xac); w2(0xa4);  in frpw_read_block_int()
128 	frpw_read_block_int(pi, buf, count, 0x08);  in frpw_read_block()
136 	case 0:  in frpw_write_block()
140 		for (k = 0; k < count; k++) {  in frpw_write_block()
148 		w2(4); w0(0xc8); cec4; w2(5);  in frpw_write_block()
149 		for (k = 0; k < count; k++)  in frpw_write_block()
155 		w2(4); w0(0xc8); cec4; w2(5);  in frpw_write_block()
156 		for (k = 0; k < count / 2; k++)  in frpw_write_block()
162 		w2(4); w0(0xc8); cec4; w2(5);  in frpw_write_block()
163 		for (k = 0; k < count / 4; k++)  in frpw_write_block()
179 	w2(4); w0(0x20); cec4;  in frpw_disconnect()
187  * returns chip_type:   0 = Xilinx, 1 = ASIC
194         w0(0); w2(8); udelay(50); w2(0xc);   /* parallel bus reset */  in frpw_test_pnp()
205 	a = r1() & 0xff; w2(4); b = r1() & 0xff;  in frpw_test_pnp()
206 	w2(0xc); w2(0xe); w2(4);  in frpw_test_pnp()
212 	return ((~a & 0x40) && (b & 0x40));  in frpw_test_pnp()
222 	int e[2] = { 0, 0 };  in frpw_test_proto()
228 	if (((pi->private & 0x1) == 0) && (pi->mode > 2)) {  in frpw_test_proto()
234 	if (((pi->private & 0x1) == 1) && (pi->mode == 2)) {  in frpw_test_proto()
240 	for (j = 0; j < 2; j++) {  in frpw_test_proto()
241 		frpw_write_regr(pi, 0, 6, 0xa0 + j * 0x10);  in frpw_test_proto()
242 		for (k = 0; k < 256; k++) {  in frpw_test_proto()
243 			frpw_write_regr(pi, 0, 2, k ^ 0xaa);  in frpw_test_proto()
244 			frpw_write_regr(pi, 0, 3, k ^ 0x55);  in frpw_test_proto()
245 			if (frpw_read_regr(pi, 0, 2) != (k ^ 0xaa))  in frpw_test_proto()
252 	frpw_read_block_int(pi, scratch, 512, 0x10);  in frpw_test_proto()
253 	r = 0;  in frpw_test_proto()
254 	for (k = 0; k < 128; k++) {  in frpw_test_proto()
261 		"frpw: port 0x%x, chip %ld, mode %d, test=(%d,%d,%d)\n",  in frpw_test_proto()
262 		pi->port, (pi->private%2), pi->mode, e[0], e[1], r);  in frpw_test_proto()
264 	return r || (e[0] && e[1]);  in frpw_test_proto()
273 		 "Freecom (%s) adapter at 0x%x, mode %d (%s), delay %d\n",  in frpw_log_adapter()
274 		 ((pi->private & 0x1) == 0) ? "Xilinx" : "ASIC",  in frpw_log_adapter()