Lines Matching +full:setup +full:- +full:duration +full:- +full:ns
8 * Copyright (C) 2005 - 2012 Cavium Inc.
31 * -- 8 bits no irq, no DMA
32 * -- 16 bits no irq, no DMA
33 * -- 16 bits True IDE mode with DMA, but no irq.
43 /* Poll interval in nS. */
78 * Compute # of eclock periods to get desired duration in in ns_to_tim_reg()
128 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_set_piomode()
150 BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); in octeon_cf_set_piomode()
154 t2--; in octeon_cf_set_piomode()
158 trh--; in octeon_cf_set_piomode()
160 pause = (int)timing.cycle - (int)timing.active - in octeon_cf_set_piomode()
161 (int)timing.setup - trh; in octeon_cf_set_piomode()
165 pause--; in octeon_cf_set_piomode()
167 octeon_cf_set_boot_reg_cfg(cf_port->cs0, div); in octeon_cf_set_piomode()
168 if (cf_port->is_true_ide) in octeon_cf_set_piomode()
170 octeon_cf_set_boot_reg_cfg(cf_port->cs1, div); in octeon_cf_set_piomode()
175 reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0)); in octeon_cf_set_piomode()
190 /* How long to hold after a write to de-assert CE. */ in octeon_cf_set_piomode()
192 /* How long to wait after a read to de-assert CE. */ in octeon_cf_set_piomode()
204 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); in octeon_cf_set_piomode()
205 if (cf_port->is_true_ide) in octeon_cf_set_piomode()
207 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), in octeon_cf_set_piomode()
213 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_set_dmamode()
227 timing = ata_timing_find_mode(dev->dma_mode); in octeon_cf_set_dmamode()
228 T0 = timing->cycle; in octeon_cf_set_dmamode()
229 Td = timing->active; in octeon_cf_set_dmamode()
230 Tkr = timing->recover; in octeon_cf_set_dmamode()
231 dma_ackh = timing->dmack_hold; in octeon_cf_set_dmamode()
234 /* dma_tim.s.tim_mult = 0 --> 4x */ in octeon_cf_set_dmamode()
239 pause = 25 - dma_arq * 1000 / in octeon_cf_set_dmamode()
244 oe_n = max(T0 - oe_a, Tkr); in octeon_cf_set_dmamode()
249 c = (cf_port->dma_base & 8) >> 3; in octeon_cf_set_dmamode()
259 * more, we use 20 nS. in octeon_cf_set_dmamode()
273 ata_dev_dbg(dev, "ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60, in octeon_cf_set_dmamode()
279 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); in octeon_cf_set_dmamode()
295 struct ata_port *ap = qc->dev->link->ap; in octeon_cf_data_xfer8()
296 void __iomem *data_addr = ap->ioaddr.data_addr; in octeon_cf_data_xfer8()
303 while (words--) { in octeon_cf_data_xfer8()
310 if (--count == 0) { in octeon_cf_data_xfer8()
311 ioread8(ap->ioaddr.altstatus_addr); in octeon_cf_data_xfer8()
334 struct ata_port *ap = qc->dev->link->ap; in octeon_cf_data_xfer16()
335 void __iomem *data_addr = ap->ioaddr.data_addr; in octeon_cf_data_xfer16()
342 while (words--) { in octeon_cf_data_xfer16()
349 if (--count == 0) { in octeon_cf_data_xfer16()
350 ioread8(ap->ioaddr.altstatus_addr); in octeon_cf_data_xfer16()
355 while (words--) { in octeon_cf_data_xfer16()
377 * Read the taskfile for 16bit non-True IDE only.
383 void __iomem *base = ap->ioaddr.data_addr; in octeon_cf_tf_read16()
386 tf->error = blob >> 8; in octeon_cf_tf_read16()
389 tf->nsect = blob & 0xff; in octeon_cf_tf_read16()
390 tf->lbal = blob >> 8; in octeon_cf_tf_read16()
393 tf->lbam = blob & 0xff; in octeon_cf_tf_read16()
394 tf->lbah = blob >> 8; in octeon_cf_tf_read16()
397 tf->device = blob & 0xff; in octeon_cf_tf_read16()
398 tf->status = blob >> 8; in octeon_cf_tf_read16()
400 if (tf->flags & ATA_TFLAG_LBA48) { in octeon_cf_tf_read16()
401 if (likely(ap->ioaddr.ctl_addr)) { in octeon_cf_tf_read16()
402 iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr); in octeon_cf_tf_read16()
405 tf->hob_feature = blob >> 8; in octeon_cf_tf_read16()
408 tf->hob_nsect = blob & 0xff; in octeon_cf_tf_read16()
409 tf->hob_lbal = blob >> 8; in octeon_cf_tf_read16()
412 tf->hob_lbam = blob & 0xff; in octeon_cf_tf_read16()
413 tf->hob_lbah = blob >> 8; in octeon_cf_tf_read16()
415 iowrite8(tf->ctl, ap->ioaddr.ctl_addr); in octeon_cf_tf_read16()
416 ap->last_ctl = tf->ctl; in octeon_cf_tf_read16()
426 void __iomem *base = ap->ioaddr.data_addr; in octeon_cf_check_status16()
435 struct ata_port *ap = link->ap; in octeon_cf_softreset16()
436 void __iomem *base = ap->ioaddr.data_addr; in octeon_cf_softreset16()
440 __raw_writew(ap->ctl, base + 0xe); in octeon_cf_softreset16()
442 __raw_writew(ap->ctl | ATA_SRST, base + 0xe); in octeon_cf_softreset16()
444 __raw_writew(ap->ctl, base + 0xe); in octeon_cf_softreset16()
453 classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err); in octeon_cf_softreset16()
458 * Load the taskfile for 16bit non-True IDE only. The device_addr is
464 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; in octeon_cf_tf_load16()
466 void __iomem *base = ap->ioaddr.data_addr; in octeon_cf_tf_load16()
468 if (tf->ctl != ap->last_ctl) { in octeon_cf_tf_load16()
469 iowrite8(tf->ctl, ap->ioaddr.ctl_addr); in octeon_cf_tf_load16()
470 ap->last_ctl = tf->ctl; in octeon_cf_tf_load16()
473 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { in octeon_cf_tf_load16()
474 __raw_writew(tf->hob_feature << 8, base + 0xc); in octeon_cf_tf_load16()
475 __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); in octeon_cf_tf_load16()
476 __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); in octeon_cf_tf_load16()
479 __raw_writew(tf->feature << 8, base + 0xc); in octeon_cf_tf_load16()
480 __raw_writew(tf->nsect | tf->lbal << 8, base + 2); in octeon_cf_tf_load16()
481 __raw_writew(tf->lbam | tf->lbah << 8, base + 4); in octeon_cf_tf_load16()
501 void __iomem *base = ap->ioaddr.data_addr; in octeon_cf_exec_command16()
504 if (tf->flags & ATA_TFLAG_DEVICE) in octeon_cf_exec_command16()
505 blob = tf->device; in octeon_cf_exec_command16()
507 blob |= (tf->command << 8); in octeon_cf_exec_command16()
519 struct ata_port *ap = qc->ap; in octeon_cf_dma_setup()
522 cf_port = ap->private_data; in octeon_cf_dma_setup()
524 qc->cursg = qc->sg; in octeon_cf_dma_setup()
525 cf_port->dma_finished = 0; in octeon_cf_dma_setup()
526 ap->ops->sff_exec_command(ap, &qc->tf); in octeon_cf_dma_setup()
530 * Start a DMA transfer that was already setup
536 struct octeon_cf_port *cf_port = qc->ap->private_data; in octeon_cf_dma_start()
542 sg = qc->cursg; in octeon_cf_dma_start()
550 cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); in octeon_cf_dma_start()
553 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); in octeon_cf_dma_start()
561 mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0); in octeon_cf_dma_start()
574 mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1; in octeon_cf_dma_start()
581 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); in octeon_cf_dma_start()
593 struct ata_eh_info *ehi = &ap->link.eh_info; in octeon_cf_dma_finished()
594 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_dma_finished()
599 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag); in octeon_cf_dma_finished()
601 if (ap->hsm_task_state != HSM_ST_LAST) in octeon_cf_dma_finished()
604 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); in octeon_cf_dma_finished()
607 qc->err_mask |= AC_ERR_HOST_BUS; in octeon_cf_dma_finished()
608 ap->hsm_task_state = HSM_ST_ERR; in octeon_cf_dma_finished()
613 dma_cfg.s.size = -1; in octeon_cf_dma_finished()
614 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); in octeon_cf_dma_finished()
618 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); in octeon_cf_dma_finished()
622 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); in octeon_cf_dma_finished()
624 status = ap->ops->sff_check_status(ap); in octeon_cf_dma_finished()
628 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA)) in octeon_cf_dma_finished()
646 spin_lock_irqsave(&host->lock, flags); in octeon_cf_interrupt()
648 for (i = 0; i < host->n_ports; i++) { in octeon_cf_interrupt()
655 ap = host->ports[i]; in octeon_cf_interrupt()
656 cf_port = ap->private_data; in octeon_cf_interrupt()
658 dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT); in octeon_cf_interrupt()
659 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); in octeon_cf_interrupt()
661 qc = ata_qc_from_tag(ap, ap->link.active_tag); in octeon_cf_interrupt()
663 if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING)) in octeon_cf_interrupt()
667 if (!sg_is_last(qc->cursg)) { in octeon_cf_interrupt()
668 qc->cursg = sg_next(qc->cursg); in octeon_cf_interrupt()
670 trace_ata_bmdma_start(ap, &qc->tf, qc->tag); in octeon_cf_interrupt()
674 cf_port->dma_finished = 1; in octeon_cf_interrupt()
677 if (!cf_port->dma_finished) in octeon_cf_interrupt()
679 status = ioread8(ap->ioaddr.altstatus_addr); in octeon_cf_interrupt()
690 cvmx_write_csr(cf_port->dma_base + DMA_INT, in octeon_cf_interrupt()
692 hrtimer_start_range_ns(&cf_port->delayed_finish, in octeon_cf_interrupt()
701 spin_unlock_irqrestore(&host->lock, flags); in octeon_cf_interrupt()
710 struct ata_port *ap = cf_port->ap; in octeon_cf_delayed_finish()
711 struct ata_host *host = ap->host; in octeon_cf_delayed_finish()
717 spin_lock_irqsave(&host->lock, flags); in octeon_cf_delayed_finish()
722 * protected by host->lock. in octeon_cf_delayed_finish()
724 if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished) in octeon_cf_delayed_finish()
727 status = ioread8(ap->ioaddr.altstatus_addr); in octeon_cf_delayed_finish()
735 qc = ata_qc_from_tag(ap, ap->link.active_tag); in octeon_cf_delayed_finish()
736 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) in octeon_cf_delayed_finish()
739 spin_unlock_irqrestore(&host->lock, flags); in octeon_cf_delayed_finish()
746 * A maximum of 2^20 - 1 16 bit transfers are possible with in octeon_cf_dev_config()
748 * (2^12 - 1 == 4095) to assure that this can never happen. in octeon_cf_dev_config()
750 dev->max_sectors = min(dev->max_sectors, 4095U); in octeon_cf_dev_config()
763 struct ata_port *ap = qc->ap; in octeon_cf_qc_issue()
765 switch (qc->tf.protocol) { in octeon_cf_qc_issue()
767 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); in octeon_cf_qc_issue()
769 trace_ata_tf_load(ap, &qc->tf); in octeon_cf_qc_issue()
770 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ in octeon_cf_qc_issue()
771 trace_ata_bmdma_setup(ap, &qc->tf, qc->tag); in octeon_cf_qc_issue()
773 trace_ata_bmdma_start(ap, &qc->tf, qc->tag); in octeon_cf_qc_issue()
775 ap->hsm_task_state = HSM_ST_LAST; in octeon_cf_qc_issue()
779 dev_err(ap->dev, "Error, ATAPI not supported\n"); in octeon_cf_qc_issue()
820 node = pdev->dev.of_node; in octeon_cf_probe()
822 return -EINVAL; in octeon_cf_probe()
824 cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL); in octeon_cf_probe()
826 return -ENOMEM; in octeon_cf_probe()
828 cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide"); in octeon_cf_probe()
830 if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0) in octeon_cf_probe()
838 cf_port->cs0 = upper_32_bits(reg); in octeon_cf_probe()
840 if (cf_port->is_true_ide) { in octeon_cf_probe()
843 "cavium,dma-engine-handle", 0); in octeon_cf_probe()
852 put_device(&dma_dev->dev); in octeon_cf_probe()
854 return -EINVAL; in octeon_cf_probe()
856 cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start, in octeon_cf_probe()
858 if (!cf_port->dma_base) { in octeon_cf_probe()
859 put_device(&dma_dev->dev); in octeon_cf_probe()
861 return -EINVAL; in octeon_cf_probe()
869 put_device(&dma_dev->dev); in octeon_cf_probe()
875 return -EINVAL; in octeon_cf_probe()
877 cs1 = devm_ioremap(&pdev->dev, res_cs1->start, in octeon_cf_probe()
880 return -EINVAL; in octeon_cf_probe()
885 cf_port->cs1 = upper_32_bits(reg); in octeon_cf_probe()
890 return -EINVAL; in octeon_cf_probe()
892 cs0 = devm_ioremap(&pdev->dev, res_cs0->start, in octeon_cf_probe()
895 return -ENOMEM; in octeon_cf_probe()
898 host = ata_host_alloc(&pdev->dev, 1); in octeon_cf_probe()
900 return -ENOMEM; in octeon_cf_probe()
902 ap = host->ports[0]; in octeon_cf_probe()
903 ap->private_data = cf_port; in octeon_cf_probe()
904 pdev->dev.platform_data = cf_port; in octeon_cf_probe()
905 cf_port->ap = ap; in octeon_cf_probe()
906 ap->ops = &octeon_cf_ops; in octeon_cf_probe()
907 ap->pio_mask = ATA_PIO6; in octeon_cf_probe()
908 ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING; in octeon_cf_probe()
912 ap->ioaddr.cmd_addr = base; in octeon_cf_probe()
913 ata_sff_std_ports(&ap->ioaddr); in octeon_cf_probe()
915 ap->ioaddr.altstatus_addr = base + 0xe; in octeon_cf_probe()
916 ap->ioaddr.ctl_addr = base + 0xe; in octeon_cf_probe()
918 } else if (cf_port->is_true_ide) { in octeon_cf_probe()
920 ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; in octeon_cf_probe()
921 ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); in octeon_cf_probe()
922 ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; in octeon_cf_probe()
923 ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; in octeon_cf_probe()
924 ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; in octeon_cf_probe()
925 ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; in octeon_cf_probe()
926 ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; in octeon_cf_probe()
927 ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; in octeon_cf_probe()
928 ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; in octeon_cf_probe()
929 ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; in octeon_cf_probe()
930 ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; in octeon_cf_probe()
931 ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; in octeon_cf_probe()
932 ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; in octeon_cf_probe()
935 ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0; in octeon_cf_probe()
937 /* True IDE mode needs a timer to poll for not-busy. */ in octeon_cf_probe()
938 hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC, in octeon_cf_probe()
940 cf_port->delayed_finish.function = octeon_cf_delayed_finish; in octeon_cf_probe()
951 ap->ioaddr.data_addr = base + ATA_REG_DATA; in octeon_cf_probe()
952 ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; in octeon_cf_probe()
953 ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; in octeon_cf_probe()
954 ap->ioaddr.ctl_addr = base + 0xe; in octeon_cf_probe()
955 ap->ioaddr.altstatus_addr = base + 0xe; in octeon_cf_probe()
957 cf_port->c0 = ap->ioaddr.ctl_addr; in octeon_cf_probe()
959 rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in octeon_cf_probe()
963 ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); in octeon_cf_probe()
965 dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n", in octeon_cf_probe()
967 cf_port->is_true_ide ? ", True IDE" : ""); in octeon_cf_probe()
980 if (cf_port->dma_base) { in octeon_cf_shutdown()
983 dma_cfg.s.size = -1; in octeon_cf_shutdown()
984 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); in octeon_cf_shutdown()
988 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); in octeon_cf_shutdown()
992 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); in octeon_cf_shutdown()
994 __raw_writeb(0, cf_port->c0); in octeon_cf_shutdown()
996 __raw_writeb(ATA_SRST, cf_port->c0); in octeon_cf_shutdown()
998 __raw_writeb(0, cf_port->c0); in octeon_cf_shutdown()
1004 { .compatible = "cavium,ebt3000-compact-flash", },
1025 MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");