Lines Matching +full:udma +full:- +full:p
1 // SPDX-License-Identifier: GPL-2.0-only
55 controller_kl_ata3, /* KeyLargo ATA-3 */
56 controller_kl_ata4, /* KeyLargo ATA-4 */
57 controller_un_ata6, /* UniNorth2 ATA-6 */
58 controller_k2_ata6, /* K2 ATA-6 */
59 controller_sh_ata6, /* Shasta ATA-6 */
65 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
66 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
67 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
68 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
69 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
73 * Extra registers, both 32-bit little-endian
88 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
89 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
107 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
112 * though I use pre-calculated tables for UDMA as usual...
136 * - Write data setup, which appears to match the cycle time. They
138 * - Ready to pause time (from spec)
139 * - Address setup. That one is weird. I don't see where exactly
140 * it fits in UDMA cycles, I got it's name from an obscure piece
230 * the BSY bit (typically some combo drives slave on the UDMA
235 * from MacOS...) --BenH.
288 { -1, 0, 0 }
300 { -1, 0, 0 }
312 { -1, 0, 0 }
329 { -1, 0, 0 }
347 { -1, 0, 0 }
366 { -1, 0, 0 }
375 for (i = 0; priv->timings[i].mode > 0; i++) { in pata_macio_find_timing()
376 if (priv->timings[i].mode == mode) in pata_macio_find_timing()
377 return &priv->timings[i]; in pata_macio_find_timing()
385 struct pata_macio_priv *priv = ap->private_data; in pata_macio_apply_timings()
386 void __iomem *rbase = ap->ioaddr.cmd_addr; in pata_macio_apply_timings()
388 if (priv->kind == controller_sh_ata6 || in pata_macio_apply_timings()
389 priv->kind == controller_un_ata6 || in pata_macio_apply_timings()
390 priv->kind == controller_k2_ata6) { in pata_macio_apply_timings()
391 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG); in pata_macio_apply_timings()
392 writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG); in pata_macio_apply_timings()
394 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG); in pata_macio_apply_timings()
408 struct pata_macio_priv *priv = ap->private_data; in pata_macio_set_timings()
411 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n", in pata_macio_set_timings()
412 adev->devno, in pata_macio_set_timings()
413 adev->pio_mode, in pata_macio_set_timings()
414 ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)), in pata_macio_set_timings()
415 adev->dma_mode, in pata_macio_set_timings()
416 ata_mode_string(ata_xfer_mode2mask(adev->dma_mode))); in pata_macio_set_timings()
419 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0; in pata_macio_set_timings()
422 t = pata_macio_find_timing(priv, adev->pio_mode); in pata_macio_set_timings()
424 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n", in pata_macio_set_timings()
425 adev->pio_mode); in pata_macio_set_timings()
431 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
434 t = pata_macio_find_timing(priv, adev->dma_mode); in pata_macio_set_timings()
435 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { in pata_macio_set_timings()
436 dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n"); in pata_macio_set_timings()
442 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
443 priv->treg[adev->devno][1] |= t->reg2; in pata_macio_set_timings()
445 dev_dbg(priv->dev, " -> %08x %08x\n", in pata_macio_set_timings()
446 priv->treg[adev->devno][0], in pata_macio_set_timings()
447 priv->treg[adev->devno][1]); in pata_macio_set_timings()
450 pata_macio_apply_timings(ap, adev->devno); in pata_macio_set_timings()
461 switch(priv->kind) { in pata_macio_default_timings()
483 priv->treg[0][0] = priv->treg[1][0] = value; in pata_macio_default_timings()
484 priv->treg[0][1] = priv->treg[1][1] = value2; in pata_macio_default_timings()
489 struct pata_macio_priv *priv = ap->private_data; in pata_macio_cable_detect()
491 /* Get cable type from device-tree */ in pata_macio_cable_detect()
492 if (priv->kind == controller_kl_ata4 || in pata_macio_cable_detect()
493 priv->kind == controller_un_ata6 || in pata_macio_cable_detect()
494 priv->kind == controller_k2_ata6 || in pata_macio_cable_detect()
495 priv->kind == controller_sh_ata6) { in pata_macio_cable_detect()
496 const char* cable = of_get_property(priv->node, "cable-type", in pata_macio_cable_detect()
503 if (cable && !strncmp(cable, "80-", 3)) { in pata_macio_cable_detect()
515 /* G5's seem to have incorrect cable type in device-tree. in pata_macio_cable_detect()
519 if (of_device_is_compatible(priv->node, "K2-UATA") || in pata_macio_cable_detect()
520 of_device_is_compatible(priv->node, "shasta-ata")) in pata_macio_cable_detect()
529 unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE); in pata_macio_qc_prep()
530 struct ata_port *ap = qc->ap; in pata_macio_qc_prep()
531 struct pata_macio_priv *priv = ap->private_data; in pata_macio_qc_prep()
536 dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n", in pata_macio_qc_prep()
537 __func__, qc, qc->flags, write, qc->dev->devno); in pata_macio_qc_prep()
539 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in pata_macio_qc_prep()
542 table = (struct dbdma_cmd *) priv->dma_table_cpu; in pata_macio_qc_prep()
545 for_each_sg(qc->sg, sg, qc->n_elem, si) { in pata_macio_qc_prep()
549 * Note h/w doesn't support 64-bit, so we unconditionally in pata_macio_qc_prep()
561 table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE); in pata_macio_qc_prep()
562 table->req_count = cpu_to_le16(len); in pata_macio_qc_prep()
563 table->phy_addr = cpu_to_le32(addr); in pata_macio_qc_prep()
564 table->cmd_dep = 0; in pata_macio_qc_prep()
565 table->xfer_status = 0; in pata_macio_qc_prep()
566 table->res_count = 0; in pata_macio_qc_prep()
568 sg_len -= len; in pata_macio_qc_prep()
579 table--; in pata_macio_qc_prep()
580 table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST); in pata_macio_qc_prep()
585 table->command = cpu_to_le16(DBDMA_STOP); in pata_macio_qc_prep()
587 dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi); in pata_macio_qc_prep()
595 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_freeze()
601 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); in pata_macio_freeze()
602 while (--timeout && (readl(&dma_regs->status) & RUN)) in pata_macio_freeze()
612 struct ata_port *ap = qc->ap; in pata_macio_bmdma_setup()
613 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_setup()
614 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_setup()
615 int dev = qc->dev->devno; in pata_macio_bmdma_setup()
617 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_setup()
620 writel(priv->dma_table_dma, &dma_regs->cmdptr); in pata_macio_bmdma_setup()
623 * UDMA reads in pata_macio_bmdma_setup()
625 if (priv->kind == controller_kl_ata4 && in pata_macio_bmdma_setup()
626 (priv->treg[dev][0] & TR_66_UDMA_EN)) { in pata_macio_bmdma_setup()
627 void __iomem *rbase = ap->ioaddr.cmd_addr; in pata_macio_bmdma_setup()
628 u32 reg = priv->treg[dev][0]; in pata_macio_bmdma_setup()
630 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) in pata_macio_bmdma_setup()
636 ap->ops->sff_exec_command(ap, &qc->tf); in pata_macio_bmdma_setup()
641 struct ata_port *ap = qc->ap; in pata_macio_bmdma_start()
642 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_start()
643 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_start()
645 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_start()
647 writel((RUN << 16) | RUN, &dma_regs->control); in pata_macio_bmdma_start()
649 (void)readl(&dma_regs->control); in pata_macio_bmdma_start()
654 struct ata_port *ap = qc->ap; in pata_macio_bmdma_stop()
655 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_stop()
656 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_stop()
659 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_stop()
662 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control); in pata_macio_bmdma_stop()
663 while (--timeout && (readl(&dma_regs->status) & RUN)) in pata_macio_bmdma_stop()
669 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_status()
670 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_status()
674 dstat = readl(&dma_regs->status); in pata_macio_bmdma_status()
676 dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat); in pata_macio_bmdma_status()
680 * - The dbdma won't stop if the command was started in pata_macio_bmdma_status()
683 * a multi-block transfer. in pata_macio_bmdma_status()
685 * - The dbdma fifo hasn't yet finished flushing to in pata_macio_bmdma_status()
700 dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__); in pata_macio_bmdma_status()
709 writel((FLUSH << 16) | FLUSH, &dma_regs->control); in pata_macio_bmdma_status()
712 dstat = readl(&dma_regs->status); in pata_macio_bmdma_status()
716 dev_warn(priv->dev, "timeout flushing DMA\n"); in pata_macio_bmdma_status()
727 struct pata_macio_priv *priv = ap->private_data; in pata_macio_port_start()
729 if (ap->ioaddr.bmdma_addr == NULL) in pata_macio_port_start()
737 priv->dma_table_cpu = in pata_macio_port_start()
738 dmam_alloc_coherent(priv->dev, in pata_macio_port_start()
740 &priv->dma_table_dma, GFP_KERNEL); in pata_macio_port_start()
741 if (priv->dma_table_cpu == NULL) { in pata_macio_port_start()
742 dev_err(priv->dev, "Unable to allocate DMA command list\n"); in pata_macio_port_start()
743 ap->ioaddr.bmdma_addr = NULL; in pata_macio_port_start()
744 ap->mwdma_mask = 0; in pata_macio_port_start()
745 ap->udma_mask = 0; in pata_macio_port_start()
752 struct pata_macio_priv *priv = ap->private_data; in pata_macio_irq_clear()
756 dev_dbgdma(priv->dev, "%s\n", __func__); in pata_macio_irq_clear()
761 dev_dbg(priv->dev, "Enabling & resetting... \n"); in pata_macio_reset_hw()
763 if (priv->mediabay) in pata_macio_reset_hw()
766 if (priv->kind == controller_ohare && !resume) { in pata_macio_reset_hw()
771 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1); in pata_macio_reset_hw()
777 priv->node, priv->aapl_bus_id, 1); in pata_macio_reset_hw()
779 priv->node, priv->aapl_bus_id, 1); in pata_macio_reset_hw()
784 priv->node, priv->aapl_bus_id, 0); in pata_macio_reset_hw()
790 if (priv->pdev && resume) { in pata_macio_reset_hw()
793 pci_restore_state(priv->pdev); in pata_macio_reset_hw()
794 rc = pcim_enable_device(priv->pdev); in pata_macio_reset_hw()
796 dev_err(&priv->pdev->dev, in pata_macio_reset_hw()
800 pci_set_master(priv->pdev); in pata_macio_reset_hw()
806 if (priv->kauai_fcr) in pata_macio_reset_hw()
809 KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr); in pata_macio_reset_hw()
818 struct ata_port *ap = ata_shost_to_port(sdev->host); in pata_macio_device_configure()
819 struct pata_macio_priv *priv = ap->private_data; in pata_macio_device_configure()
830 dev = &ap->link.device[sdev->id]; in pata_macio_device_configure()
833 if (priv->kind == controller_ohare) { in pata_macio_device_configure()
834 lim->dma_alignment = 31; in pata_macio_device_configure()
835 lim->dma_pad_mask = 31; in pata_macio_device_configure()
843 if (dev->class != ATA_DEV_ATAPI) in pata_macio_device_configure()
847 if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) { in pata_macio_device_configure()
849 lim->dma_alignment = 15; in pata_macio_device_configure()
850 lim->dma_pad_mask = 15; in pata_macio_device_configure()
855 * to do the same Apple does and pray they did not get it wrong :-) in pata_macio_device_configure()
857 BUG_ON(!priv->pdev); in pata_macio_device_configure()
858 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08); in pata_macio_device_configure()
859 pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd); in pata_macio_device_configure()
860 pci_write_config_word(priv->pdev, PCI_COMMAND, in pata_macio_device_configure()
874 ata_host_suspend(priv->host, mesg); in pata_macio_do_suspend()
881 disable_irq(priv->irq); in pata_macio_do_suspend()
884 if (priv->mediabay) in pata_macio_do_suspend()
888 if (priv->kauai_fcr) { in pata_macio_do_suspend()
889 u32 fcr = readl(priv->kauai_fcr); in pata_macio_do_suspend()
891 writel(fcr, priv->kauai_fcr); in pata_macio_do_suspend()
899 if (priv->pdev) { in pata_macio_do_suspend()
900 pci_save_state(priv->pdev); in pata_macio_do_suspend()
901 pci_disable_device(priv->pdev); in pata_macio_do_suspend()
905 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, in pata_macio_do_suspend()
906 priv->aapl_bus_id, 0); in pata_macio_do_suspend()
913 /* Reset and re-enable the HW */ in pata_macio_do_resume()
917 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_do_resume()
920 enable_irq(priv->irq); in pata_macio_do_resume()
923 ata_host_resume(priv->host); in pata_macio_do_resume()
963 if (of_device_is_compatible(priv->node, "shasta-ata")) { in pata_macio_invariants()
964 priv->kind = controller_sh_ata6; in pata_macio_invariants()
965 priv->timings = pata_macio_shasta_timings; in pata_macio_invariants()
966 } else if (of_device_is_compatible(priv->node, "kauai-ata")) { in pata_macio_invariants()
967 priv->kind = controller_un_ata6; in pata_macio_invariants()
968 priv->timings = pata_macio_kauai_timings; in pata_macio_invariants()
969 } else if (of_device_is_compatible(priv->node, "K2-UATA")) { in pata_macio_invariants()
970 priv->kind = controller_k2_ata6; in pata_macio_invariants()
971 priv->timings = pata_macio_kauai_timings; in pata_macio_invariants()
972 } else if (of_device_is_compatible(priv->node, "keylargo-ata")) { in pata_macio_invariants()
973 if (of_node_name_eq(priv->node, "ata-4")) { in pata_macio_invariants()
974 priv->kind = controller_kl_ata4; in pata_macio_invariants()
975 priv->timings = pata_macio_kl66_timings; in pata_macio_invariants()
977 priv->kind = controller_kl_ata3; in pata_macio_invariants()
978 priv->timings = pata_macio_kl33_timings; in pata_macio_invariants()
980 } else if (of_device_is_compatible(priv->node, "heathrow-ata")) { in pata_macio_invariants()
981 priv->kind = controller_heathrow; in pata_macio_invariants()
982 priv->timings = pata_macio_heathrow_timings; in pata_macio_invariants()
984 priv->kind = controller_ohare; in pata_macio_invariants()
985 priv->timings = pata_macio_ohare_timings; in pata_macio_invariants()
988 /* XXX FIXME --- setup priv->mediabay here */ in pata_macio_invariants()
991 bidp = of_get_property(priv->node, "AAPL,bus-id", NULL); in pata_macio_invariants()
992 priv->aapl_bus_id = bidp ? *bidp : 0; in pata_macio_invariants()
994 /* Fixup missing Apple bus ID in case of media-bay */ in pata_macio_invariants()
995 if (priv->mediabay && !bidp) in pata_macio_invariants()
996 priv->aapl_bus_id = 1; in pata_macio_invariants()
1003 ioaddr->cmd_addr = base; in pata_macio_setup_ios()
1006 ioaddr->data_addr = base + (ATA_REG_DATA << 4); in pata_macio_setup_ios()
1007 ioaddr->error_addr = base + (ATA_REG_ERR << 4); in pata_macio_setup_ios()
1008 ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4); in pata_macio_setup_ios()
1009 ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4); in pata_macio_setup_ios()
1010 ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4); in pata_macio_setup_ios()
1011 ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4); in pata_macio_setup_ios()
1012 ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4); in pata_macio_setup_ios()
1013 ioaddr->device_addr = base + (ATA_REG_DEVICE << 4); in pata_macio_setup_ios()
1014 ioaddr->status_addr = base + (ATA_REG_STATUS << 4); in pata_macio_setup_ios()
1015 ioaddr->command_addr = base + (ATA_REG_CMD << 4); in pata_macio_setup_ios()
1016 ioaddr->altstatus_addr = base + 0x160; in pata_macio_setup_ios()
1017 ioaddr->ctl_addr = base + 0x160; in pata_macio_setup_ios()
1018 ioaddr->bmdma_addr = dma; in pata_macio_setup_ios()
1026 pinfo->pio_mask = 0; in pmac_macio_calc_timing_masks()
1027 pinfo->mwdma_mask = 0; in pmac_macio_calc_timing_masks()
1028 pinfo->udma_mask = 0; in pmac_macio_calc_timing_masks()
1030 while (priv->timings[i].mode > 0) { in pmac_macio_calc_timing_masks()
1031 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); in pmac_macio_calc_timing_masks()
1032 switch(priv->timings[i].mode & 0xf0) { in pmac_macio_calc_timing_masks()
1034 pinfo->pio_mask |= (mask >> 8); in pmac_macio_calc_timing_masks()
1037 pinfo->mwdma_mask |= mask; in pmac_macio_calc_timing_masks()
1039 case 0x40: /* UDMA */ in pmac_macio_calc_timing_masks()
1040 pinfo->udma_mask |= mask; in pmac_macio_calc_timing_masks()
1045 dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n", in pmac_macio_calc_timing_masks()
1046 pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask); in pmac_macio_calc_timing_masks()
1060 * device-tree in pata_macio_common_init()
1074 priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1); in pata_macio_common_init()
1075 if (priv->host == NULL) { in pata_macio_common_init()
1076 dev_err(priv->dev, "Failed to allocate ATA port structure\n"); in pata_macio_common_init()
1077 return -ENOMEM; in pata_macio_common_init()
1081 priv->host->private_data = priv; in pata_macio_common_init()
1084 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100); in pata_macio_common_init()
1085 if (priv->tfregs == NULL) { in pata_macio_common_init()
1086 dev_err(priv->dev, "Failed to map ATA ports\n"); in pata_macio_common_init()
1087 return -ENOMEM; in pata_macio_common_init()
1089 priv->host->iomap = &priv->tfregs; in pata_macio_common_init()
1093 dma_regs = devm_ioremap(priv->dev, dmaregs, in pata_macio_common_init()
1096 dev_warn(priv->dev, "Failed to map ATA DMA registers\n"); in pata_macio_common_init()
1101 priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4); in pata_macio_common_init()
1102 if (priv->kauai_fcr == NULL) { in pata_macio_common_init()
1103 dev_err(priv->dev, "Failed to map ATA FCR register\n"); in pata_macio_common_init()
1104 return -ENOMEM; in pata_macio_common_init()
1109 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr, in pata_macio_common_init()
1110 priv->tfregs, dma_regs); in pata_macio_common_init()
1111 priv->host->ports[0]->private_data = priv; in pata_macio_common_init()
1113 /* hard-reset the controller */ in pata_macio_common_init()
1115 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_common_init()
1118 if (priv->pdev && dma_regs) in pata_macio_common_init()
1119 pci_set_master(priv->pdev); in pata_macio_common_init()
1121 dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n", in pata_macio_common_init()
1122 macio_ata_names[priv->kind], priv->aapl_bus_id); in pata_macio_common_init()
1125 priv->irq = irq; in pata_macio_common_init()
1126 return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0, in pata_macio_common_init()
1138 /* Check for broken device-trees */ in pata_macio_attach()
1140 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1142 return -ENXIO; in pata_macio_attach()
1149 priv = devm_kzalloc(&mdev->ofdev.dev, in pata_macio_attach()
1152 return -ENOMEM; in pata_macio_attach()
1154 priv->node = of_node_get(mdev->ofdev.dev.of_node); in pata_macio_attach()
1155 priv->mdev = mdev; in pata_macio_attach()
1156 priv->dev = &mdev->ofdev.dev; in pata_macio_attach()
1159 if (macio_request_resource(mdev, 0, "pata-macio")) { in pata_macio_attach()
1160 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1162 return -EBUSY; in pata_macio_attach()
1168 if (macio_request_resource(mdev, 1, "pata-macio-dma")) in pata_macio_attach()
1169 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1177 * device-trees. in pata_macio_attach()
1179 * This is a bit bogus, it should be fixed in the device-tree itself, in pata_macio_attach()
1185 dev_warn(&mdev->ofdev.dev, in pata_macio_attach()
1192 lock_media_bay(priv->mdev->media_bay); in pata_macio_attach()
1200 unlock_media_bay(priv->mdev->media_bay); in pata_macio_attach()
1208 struct pata_macio_priv *priv = host->private_data; in pata_macio_detach()
1210 lock_media_bay(priv->mdev->media_bay); in pata_macio_detach()
1215 priv->host->private_data = NULL; in pata_macio_detach()
1219 unlock_media_bay(priv->mdev->media_bay); in pata_macio_detach()
1227 return pata_macio_do_suspend(host->private_data, mesg); in pata_macio_suspend()
1234 return pata_macio_do_resume(host->private_data); in pata_macio_resume()
1247 if (!host || !host->private_data) in pata_macio_mb_event()
1249 ap = host->ports[0]; in pata_macio_mb_event()
1250 spin_lock_irqsave(ap->lock, flags); in pata_macio_mb_event()
1251 ehi = &ap->link.eh_info; in pata_macio_mb_event()
1258 ata_for_each_dev(dev, &ap->link, ALL) in pata_macio_mb_event()
1259 dev->flags |= ATA_DFLAG_DETACH; in pata_macio_mb_event()
1262 spin_unlock_irqrestore(ap->lock, flags); in pata_macio_mb_event()
1278 dev_err(&pdev->dev, in pata_macio_pci_attach()
1280 return -ENODEV; in pata_macio_pci_attach()
1285 dev_err(&pdev->dev, in pata_macio_pci_attach()
1287 return -ENXIO; in pata_macio_pci_attach()
1291 priv = devm_kzalloc(&pdev->dev, in pata_macio_pci_attach()
1294 return -ENOMEM; in pata_macio_pci_attach()
1296 priv->node = of_node_get(np); in pata_macio_pci_attach()
1297 priv->pdev = pdev; in pata_macio_pci_attach()
1298 priv->dev = &pdev->dev; in pata_macio_pci_attach()
1301 if (pci_request_regions(pdev, "pata-macio")) { in pata_macio_pci_attach()
1302 dev_err(&pdev->dev, in pata_macio_pci_attach()
1304 return -EBUSY; in pata_macio_pci_attach()
1313 pdev->irq)) in pata_macio_pci_attach()
1314 return -ENXIO; in pata_macio_pci_attach()
1331 return pata_macio_do_suspend(host->private_data, mesg); in pata_macio_pci_suspend()
1338 return pata_macio_do_resume(host->private_data); in pata_macio_pci_resume()
1355 .name = "pata-macio",
1380 .name = "pata-pci-macio",
1397 return -ENODEV; in pata_macio_init()