Lines Matching +full:0 +full:x00084000
45 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
75 #define IDE_TIMING_CONFIG 0x200
76 #define IDE_INTERRUPT 0x300
79 #define IDE_KAUAI_PIO_CONFIG 0x200
80 #define IDE_KAUAI_ULTRA_CONFIG 0x210
81 #define IDE_KAUAI_POLL_CONFIG 0x220
98 #define TR_133_PIOREG_PIO_MASK 0xff000fff
99 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
100 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
101 #define TR_133_UDMAREG_UDMA_EN 0x00000001
114 #define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
116 #define TR_100_MDMA_MASK 0x00fff000
117 #define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
119 #define TR_100_MDMA_ACCESS_MASK 0x0003f000
121 #define TR_100_PIO_MASK 0xff000fff
122 #define TR_100_PIO_RECOVERY_MASK 0x00000fc0
124 #define TR_100_PIO_ACCESS_MASK 0x0000003f
125 #define TR_100_PIO_ACCESS_SHIFT 0
127 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
128 #define TR_100_UDMAREG_UDMA_EN 0x00000001
131 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
141 * of commented out code in Darwin. They leave it to 0, we do as
147 #define TR_66_UDMA_MASK 0xfff00000
148 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
149 #define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
151 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
153 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
155 #define TR_66_MDMA_MASK 0x000ffc00
156 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
158 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
160 #define TR_66_PIO_MASK 0xe00003ff
161 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
163 #define TR_66_PIO_ACCESS_MASK 0x0000001f
164 #define TR_66_PIO_ACCESS_SHIFT 0
174 * implementation afaik. The E bit appears to be set for PIO mode 0 and
177 #define TR_33_MDMA_MASK 0x003ff800
178 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
180 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
182 #define TR_33_MDMA_HALFTICK 0x00200000
183 #define TR_33_PIO_MASK 0x000007ff
184 #define TR_33_PIO_E 0x00000400
185 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
187 #define TR_33_PIO_ACCESS_MASK 0x0000001f
188 #define TR_33_PIO_ACCESS_SHIFT 0
194 #define IDE_INTR_DMA 0x80000000
195 #define IDE_INTR_DEVICE 0x40000000
198 * FCR Register on Kauai. Not sure what bit 0x4 is ...
200 #define KAUAI_FCR_UATA_MAGIC 0x00000004
201 #define KAUAI_FCR_UATA_RESET_N 0x00000002
202 #define KAUAI_FCR_UATA_ENABLE 0x00000001
209 #define MAX_DBDMA_SEG 0xff00
280 { XFER_PIO_0, 0x00000526, 0, },
281 { XFER_PIO_1, 0x00000085, 0, },
282 { XFER_PIO_2, 0x00000025, 0, },
283 { XFER_PIO_3, 0x00000025, 0, },
284 { XFER_PIO_4, 0x00000025, 0, },
285 { XFER_MW_DMA_0, 0x00074000, 0, },
286 { XFER_MW_DMA_1, 0x00221000, 0, },
287 { XFER_MW_DMA_2, 0x00211000, 0, },
288 { -1, 0, 0 }
292 { XFER_PIO_0, 0x00000526, 0, },
293 { XFER_PIO_1, 0x00000085, 0, },
294 { XFER_PIO_2, 0x00000025, 0, },
295 { XFER_PIO_3, 0x00000025, 0, },
296 { XFER_PIO_4, 0x00000025, 0, },
297 { XFER_MW_DMA_0, 0x00074000, 0, },
298 { XFER_MW_DMA_1, 0x00221000, 0, },
299 { XFER_MW_DMA_2, 0x00211000, 0, },
300 { -1, 0, 0 }
304 { XFER_PIO_0, 0x00000526, 0, },
305 { XFER_PIO_1, 0x00000085, 0, },
306 { XFER_PIO_2, 0x00000025, 0, },
307 { XFER_PIO_3, 0x00000025, 0, },
308 { XFER_PIO_4, 0x00000025, 0, },
309 { XFER_MW_DMA_0, 0x00084000, 0, },
310 { XFER_MW_DMA_1, 0x00021800, 0, },
311 { XFER_MW_DMA_2, 0x00011800, 0, },
312 { -1, 0, 0 }
316 { XFER_PIO_0, 0x0000038c, 0, },
317 { XFER_PIO_1, 0x0000020a, 0, },
318 { XFER_PIO_2, 0x00000127, 0, },
319 { XFER_PIO_3, 0x000000c6, 0, },
320 { XFER_PIO_4, 0x00000065, 0, },
321 { XFER_MW_DMA_0, 0x00084000, 0, },
322 { XFER_MW_DMA_1, 0x00029800, 0, },
323 { XFER_MW_DMA_2, 0x00019400, 0, },
324 { XFER_UDMA_0, 0x19100000, 0, },
325 { XFER_UDMA_1, 0x14d00000, 0, },
326 { XFER_UDMA_2, 0x10900000, 0, },
327 { XFER_UDMA_3, 0x0c700000, 0, },
328 { XFER_UDMA_4, 0x0c500000, 0, },
329 { -1, 0, 0 }
333 { XFER_PIO_0, 0x08000a92, 0, },
334 { XFER_PIO_1, 0x0800060f, 0, },
335 { XFER_PIO_2, 0x0800038b, 0, },
336 { XFER_PIO_3, 0x05000249, 0, },
337 { XFER_PIO_4, 0x04000148, 0, },
338 { XFER_MW_DMA_0, 0x00618000, 0, },
339 { XFER_MW_DMA_1, 0x00209000, 0, },
340 { XFER_MW_DMA_2, 0x00148000, 0, },
341 { XFER_UDMA_0, 0, 0x000070c1, },
342 { XFER_UDMA_1, 0, 0x00005d81, },
343 { XFER_UDMA_2, 0, 0x00004a61, },
344 { XFER_UDMA_3, 0, 0x00003a51, },
345 { XFER_UDMA_4, 0, 0x00002a31, },
346 { XFER_UDMA_5, 0, 0x00002921, },
347 { -1, 0, 0 }
351 { XFER_PIO_0, 0x0a000c97, 0, },
352 { XFER_PIO_1, 0x07000712, 0, },
353 { XFER_PIO_2, 0x040003cd, 0, },
354 { XFER_PIO_3, 0x0500028b, 0, },
355 { XFER_PIO_4, 0x0400010a, 0, },
356 { XFER_MW_DMA_0, 0x00820800, 0, },
357 { XFER_MW_DMA_1, 0x0028b000, 0, },
358 { XFER_MW_DMA_2, 0x001ca000, 0, },
359 { XFER_UDMA_0, 0, 0x00035901, },
360 { XFER_UDMA_1, 0, 0x000348b1, },
361 { XFER_UDMA_2, 0, 0x00033881, },
362 { XFER_UDMA_3, 0, 0x00033861, },
363 { XFER_UDMA_4, 0, 0x00033841, },
364 { XFER_UDMA_5, 0, 0x00033031, },
365 { XFER_UDMA_6, 0, 0x00033021, },
366 { -1, 0, 0 }
375 for (i = 0; priv->timings[i].mode > 0; i++) { in pata_macio_find_timing()
391 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG); in pata_macio_apply_timings()
394 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG); in pata_macio_apply_timings()
411 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n", in pata_macio_set_timings()
419 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0; in pata_macio_set_timings()
424 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n", in pata_macio_set_timings()
431 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
435 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { in pata_macio_set_timings()
442 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
446 priv->treg[adev->devno][0], in pata_macio_set_timings()
459 unsigned int value, value2 = 0; in pata_macio_default_timings()
463 value = 0x0a820c97; in pata_macio_default_timings()
464 value2 = 0x00033031; in pata_macio_default_timings()
468 value = 0x08618a92; in pata_macio_default_timings()
469 value2 = 0x00002921; in pata_macio_default_timings()
472 value = 0x0008438c; in pata_macio_default_timings()
475 value = 0x00084526; in pata_macio_default_timings()
480 value = 0x00074526; in pata_macio_default_timings()
483 priv->treg[0][0] = priv->treg[1][0] = value; in pata_macio_default_timings()
484 priv->treg[0][1] = priv->treg[1][1] = value2; in pata_macio_default_timings()
544 pi = 0; in pata_macio_qc_prep()
564 table->cmd_dep = 0; in pata_macio_qc_prep()
565 table->xfer_status = 0; in pata_macio_qc_prep()
566 table->res_count = 0; in pata_macio_qc_prep()
584 memset(table, 0, sizeof(struct dbdma_cmd)); in pata_macio_qc_prep()
626 (priv->treg[dev][0] & TR_66_UDMA_EN)) { in pata_macio_bmdma_setup()
628 u32 reg = priv->treg[dev][0]; in pata_macio_bmdma_setup()
631 reg += 0x00800000; in pata_macio_bmdma_setup()
672 unsigned long timeout = 0; in pata_macio_bmdma_status()
697 if ((dstat & ACTIVE) == 0) in pata_macio_bmdma_status()
713 if ((dstat & FLUSH) == 0) in pata_macio_bmdma_status()
730 return 0; in pata_macio_port_start()
744 ap->mwdma_mask = 0; in pata_macio_port_start()
745 ap->udma_mask = 0; in pata_macio_port_start()
747 return 0; in pata_macio_port_start()
771 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1); in pata_macio_reset_hw()
782 if (rc == 0) { in pata_macio_reset_hw()
784 priv->node, priv->aapl_bus_id, 0); in pata_macio_reset_hw()
839 return 0; in pata_macio_device_configure()
844 return 0; in pata_macio_device_configure()
858 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08); in pata_macio_device_configure()
867 return 0; in pata_macio_device_configure()
885 return 0; in pata_macio_do_suspend()
906 priv->aapl_bus_id, 0); in pata_macio_do_suspend()
908 return 0; in pata_macio_do_suspend()
917 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_do_resume()
925 return 0; in pata_macio_do_resume()
992 priv->aapl_bus_id = bidp ? *bidp : 0; in pata_macio_invariants()
1016 ioaddr->altstatus_addr = base + 0x160; in pata_macio_setup_ios()
1017 ioaddr->ctl_addr = base + 0x160; in pata_macio_setup_ios()
1024 int i = 0; in pmac_macio_calc_timing_masks()
1026 pinfo->pio_mask = 0; in pmac_macio_calc_timing_masks()
1027 pinfo->mwdma_mask = 0; in pmac_macio_calc_timing_masks()
1028 pinfo->udma_mask = 0; in pmac_macio_calc_timing_masks()
1030 while (priv->timings[i].mode > 0) { in pmac_macio_calc_timing_masks()
1031 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); in pmac_macio_calc_timing_masks()
1032 switch(priv->timings[i].mode & 0xf0) { in pmac_macio_calc_timing_masks()
1033 case 0x00: /* PIO */ in pmac_macio_calc_timing_masks()
1036 case 0x20: /* MWDMA */ in pmac_macio_calc_timing_masks()
1039 case 0x40: /* UDMA */ in pmac_macio_calc_timing_masks()
1068 memset(&pinfo, 0, sizeof(struct ata_port_info)); in pata_macio_common_init()
1084 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100); in pata_macio_common_init()
1092 if (dmaregs != 0) { in pata_macio_common_init()
1100 if (fcregs != 0) { in pata_macio_common_init()
1109 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr, in pata_macio_common_init()
1111 priv->host->ports[0]->private_data = priv; in pata_macio_common_init()
1114 pata_macio_reset_hw(priv, 0); in pata_macio_common_init()
1115 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_common_init()
1126 return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0, in pata_macio_common_init()
1134 resource_size_t tfregs, dmaregs = 0; in pata_macio_attach()
1139 if (macio_resource_count(mdev) == 0) { in pata_macio_attach()
1159 if (macio_request_resource(mdev, 0, "pata-macio")) { in pata_macio_attach()
1164 tfregs = macio_resource_start(mdev, 0); in pata_macio_attach()
1184 if (macio_irq_count(mdev) == 0) { in pata_macio_attach()
1189 irq = macio_irq(mdev, 0); in pata_macio_attach()
1198 0, /* Feature control */ in pata_macio_attach()
1249 ap = host->ports[0]; in pata_macio_mb_event()
1308 rbase = pci_resource_start(pdev, 0); in pata_macio_pci_attach()
1310 rbase + 0x2000, /* Taskfile regs */ in pata_macio_pci_attach()
1311 rbase + 0x1000, /* DBDMA regs */ in pata_macio_pci_attach()
1316 return 0; in pata_macio_pci_attach()
1371 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1372 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1373 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1374 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1375 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1407 return 0; in pata_macio_init()