43 	pci_read_config_dword(pdev, 0x44, &r1);  in hpt3x3_set_piomode()
44 	pci_read_config_dword(pdev, 0x48, &r2);  in hpt3x3_set_piomode()
48 	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */  in hpt3x3_set_piomode()
50 	pci_write_config_dword(pdev, 0x44, r1);  in hpt3x3_set_piomode()
51 	pci_write_config_dword(pdev, 0x48, r2);  in hpt3x3_set_piomode()
63  *	0x44 : bit 0-2 master mode, 3-5 slave mode, etc
64  *	0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
72 	int mode_num = adev->dma_mode & 0x0F;  in hpt3x3_set_dmamode()
74 	pci_read_config_dword(pdev, 0x44, &r1);  in hpt3x3_set_dmamode()
75 	pci_read_config_dword(pdev, 0x48, &r2);  in hpt3x3_set_dmamode()
79 	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */  in hpt3x3_set_dmamode()
82 		r2 |= (0x01 << dn);	/* Ultra mode */  in hpt3x3_set_dmamode()
84 		r2 |= (0x10 << dn);	/* MWDMA */  in hpt3x3_set_dmamode()
86 	pci_write_config_dword(pdev, 0x44, r1);  in hpt3x3_set_dmamode()
87 	pci_write_config_dword(pdev, 0x48, r2);  in hpt3x3_set_dmamode()
167 	pci_write_config_word(dev, 0x80, 0x00);  in hpt3x3_init_chipset()
171 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);  in hpt3x3_init_chipset()
173 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);  in hpt3x3_init_chipset()
198 	static const u8 offset_cmd[2] = { 0x20, 0x28 };  in hpt3x3_init_one()
199 	static const u8 offset_ctl[2] = { 0x36, 0x3E };  in hpt3x3_init_one()
230 	for (i = 0; i < host->n_ports; i++) {  in hpt3x3_init_one()
262 	return 0;  in hpt3x3_reinit_one()