41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
203 	"AHCI Enclosure Management Message control (0 = off, 1 = on)");
223 	for (i = 0; i < 5; i++) {  in ahci_enable_ahci()
350 	for (i = 0; i < count; i += 4) {  in ahci_read_em_buffer()
352 		buf[i] = msg & 0xff;  in ahci_read_em_buffer()
353 		buf[i + 1] = (msg >> 8) & 0xff;  in ahci_read_em_buffer()
354 		buf[i + 2] = (msg >> 16) & 0xff;  in ahci_read_em_buffer()
355 		buf[i + 3] = (msg >> 24) & 0xff;  in ahci_read_em_buffer()
394 	for (i = 0; i < size; i += 4) {  in ahci_store_em_buffer()
475 	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))  in ahci_save_initial_config()
478 		hpriv->saved_cap2 = cap2 = 0;  in ahci_save_initial_config()
537 		dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",  in ahci_save_initial_config()
545 		dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",  in ahci_save_initial_config()
553 		int map_ports = 0;  in ahci_save_initial_config()
555 		for (i = 0; i < AHCI_MAX_PORTS; i++)  in ahci_save_initial_config()
564 				 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",  in ahci_save_initial_config()
566 			port_map = 0;  in ahci_save_initial_config()
571 	if (!port_map && vers < 0x10300) {  in ahci_save_initial_config()
573 		dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);  in ahci_save_initial_config()
653 	return 0;  in ahci_scr_offset()
663 		return 0;  in ahci_scr_read()
675 		return 0;  in ahci_scr_write()
715 	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)  in ahci_stop_engine()
716 		return 0;  in ahci_stop_engine()
723 	if (tmp == 0xffffffff) {  in ahci_stop_engine()
738 	return 0;  in ahci_stop_engine()
753 	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);  in ahci_start_fis_rx()
758 	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);  in ahci_start_fis_rx()
786 	return 0;  in ahci_stop_fis_rx()
845 				return 0;  in ahci_set_lpm()
877 	return 0;  in ahci_set_lpm()
890 	/* put device into listen mode, first set PxSCTL.DET to 0 */  in ahci_power_down()
892 	scontrol &= ~0xf;  in ahci_power_down()
895 	/* then set PxCMD.SUD to 0 */  in ahci_power_down()
924 			for (i = 0; i < EM_MAX_RETRY; i++) {  in ahci_start_port()
969 	return 0;  in ahci_deinit_port()
987 		return 0;  in ahci_reset_controller()
998 	 * bit is read to be "0". Reset must complete within 1 second, or the  in ahci_reset_controller()
1004 		dev_err(host->dev, "Controller reset failed (0x%x)\n",  in ahci_reset_controller()
1016 	return 0;  in ahci_reset_controller()
1058 			activity_led_state = 0;  in ahci_sw_activity_blink()
1085 	emp->saved_activity = emp->activity = 0;  in ahci_init_sw_activity()
1087 	timer_setup(&emp->timer, ahci_sw_activity_blink, 0);  in ahci_init_sw_activity()
1105 	return 0;  in ahci_reset_em()
1116 	u32 message[] = {0, 0};  in ahci_transmit_led_message()
1147 		message[0] |= (4 << 8);  in ahci_transmit_led_message()
1149 		/* ignore 0:4 of byte zero, fill in port info yourself */  in ahci_transmit_led_message()
1153 		writel(message[0], mmio + hpriv->em_loc);  in ahci_transmit_led_message()
1176 	int rc = 0;  in ahci_led_show()
1193 	if (kstrtouint(buf, 0, &state) < 0)  in ahci_led_store()
1243 	return 0;  in ahci_activity_store()
1267 	dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);  in ahci_port_clear_pending_irq()
1272 	dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);  in ahci_port_clear_pending_irq()
1302 	for (i = 0; i < host->n_ports; i++) {  in ahci_init_controller()
1313 	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);  in ahci_init_controller()
1316 	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);  in ahci_init_controller()
1338 	tf.lbah		= (tmp >> 24)	& 0xff;  in ahci_dev_classify()
1339 	tf.lbam		= (tmp >> 16)	& 0xff;  in ahci_dev_classify()
1340 	tf.lbal		= (tmp >> 8)	& 0xff;  in ahci_dev_classify()
1341 	tf.nsect	= (tmp)		& 0xff;  in ahci_dev_classify()
1355 	pp->cmd_slot[tag].status = 0;  in ahci_fill_cmd_slot()
1356 	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);  in ahci_fill_cmd_slot()
1365 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;  in ahci_kick_engine()
1379 		rc = 0;  in ahci_kick_engine()
1393 	rc = 0;  in ahci_kick_engine()
1418 	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));  in ahci_exec_polled_cmd()
1434 					0x1, 0x1, 1, timeout_msec);  in ahci_exec_polled_cmd()
1435 		if (tmp & 0x1) {  in ahci_exec_polled_cmd()
1442 	return 0;  in ahci_exec_polled_cmd()
1466 	 * clear PxFBS.EN to '0' prior to issuing software reset to devices  in ahci_do_softreset()
1477 	msecs = 0;  in ahci_do_softreset()
1483 	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,  in ahci_do_softreset()
1495 	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);  in ahci_do_softreset()
1518 	return 0;  in ahci_do_softreset()
1528 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;  in ahci_check_ready()
1546 	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;  in ahci_bad_pmp_check_ready()
1574 	 * again to port 0.  in ahci_pmp_retry_softreset()
1582 			rc = ahci_do_softreset(link, class, 0, deadline,  in ahci_pmp_retry_softreset()
1606 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);  in ahci_do_hardreset()
1663 		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);  in ahci_fill_sg()
1700 		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);  in ahci_qc_prep()
1704 	n_elem = 0;  in ahci_qc_prep()
1780 	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);  in ahci_error_intr()
1812 				  unk[0], unk[1], unk[2], unk[3]);  in ahci_error_intr()
1860 	u32 qc_active = 0;  in ahci_qc_complete()
1882 	if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) {  in ahci_qc_complete()
1928 			/* If the 'N' bit in word 0 of the FIS is set,  in ahci_handle_port_interrupt()
1940 				u32 f0 = le32_to_cpu(f[0]);  in ahci_handle_port_interrupt()
1980 	unsigned int i, handled = 0;  in ahci_handle_port_intr()
1982 	for (i = 0; i < host->n_ports; i++) {  in ahci_handle_port_intr()
2008 	unsigned int rc = 0;  in ahci_single_level_irq_intr()
2015 	/* sigh.  0xffffffff is a valid return from h/w */  in ahci_single_level_irq_intr()
2069 	return 0;  in ahci_qc_issue()
2188 	writel(0, port_mmio + PORT_IRQ_MASK);  in ahci_freeze()
2265 	if (dito > 0x3ff)  in ahci_set_aggressive_devslp()
2266 		dito = 0x3ff;  in ahci_set_aggressive_devslp()
2268 	dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;  in ahci_set_aggressive_devslp()
2296 	/* Make dito, mdat, deto bits to 0s */  in ahci_set_aggressive_devslp()
2360 	if ((fbs & PORT_FBS_EN) == 0) {  in ahci_disable_fbs()
2438 	return 0;  in ahci_port_resume()
2461 	if (rc == 0)  in ahci_port_suspend()
2604 	speed = (cap >> 20) & 0xf;  in ahci_print_info()
2619 		(vers >> 24) & 0xff,  in ahci_print_info()
2620 		(vers >> 16) & 0xff,  in ahci_print_info()
2621 		(vers >> 8) & 0xff,  in ahci_print_info()
2622 		vers & 0xff,  in ahci_print_info()
2624 		((cap >> 8) & 0x1f) + 1,  in ahci_print_info()
2629 		"%u/%u ports implemented (port mask 0x%x)\n"  in ahci_print_info()
2633 		(cap & 0x1f) + 1,  in ahci_print_info()
2687 		hpriv->em_buf_sz = ((em_loc & 0xff) * 4);  in ahci_set_em_messages()
2709 	for (i = 0; i < host->n_ports; i++) {  in ahci_host_activate_multi_irqs()
2720 				0, pp->irq_desc, host->ports[i]);  in ahci_host_activate_multi_irqs()
2739  *	0 on success, -errno otherwise.