26 #define SATA_ENET_CONFIG_REG		0x00000000
27 #define  CFG_SATA_ENET_SELECT_MASK	0x00000001
30 #define SLVRDERRATTRIBUTES		0x00000000
31 #define SLVWRERRATTRIBUTES		0x00000004
32 #define MSTRDERRATTRIBUTES		0x00000008
33 #define MSTWRERRATTRIBUTES		0x0000000c
34 #define BUSCTLREG			0x00000014
35 #define IOFMSTRWAUX			0x00000018
36 #define INTSTATUSMASK			0x0000002c
37 #define ERRINTSTATUS			0x00000030
38 #define ERRINTSTATUSMASK		0x00000034
41 #define PORTCFG				0x000000a4
43 		(((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
44 #define PORTPHY1CFG		0x000000a8
46 		(((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
47 #define PORTPHY2CFG			0x000000ac
48 #define PORTPHY3CFG			0x000000b0
49 #define PORTPHY4CFG			0x000000b4
50 #define PORTPHY5CFG			0x000000b8
51 #define SCTL0				0x0000012C
53 		(((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
55 		(((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
56 #define PORTAXICFG			0x000000bc
58 		(((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
59 #define PORTRANSCFG			0x000000c8
61 		(((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
64 #define INT_SLV_TMOMASK			0x00000010
67 #define CFG_MEM_RAM_SHUTDOWN		0x00000070
68 #define BLOCK_MEM_RDY			0x00000074
92 	writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);  in xgene_ahci_init_memram()
95 	if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {  in xgene_ahci_init_memram()
99 	return 0;  in xgene_ahci_init_memram()
149 				    PORT_CMD_ISSUE, 0x0, 1, 100))  in xgene_ahci_restart_engine()
167 	return 0;  in xgene_ahci_restart_engine()
191 	int rc = 0;  in xgene_ahci_qc_issue()
223 	return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&  in xgene_ahci_is_memram_inited()
224 	        readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);  in xgene_ahci_is_memram_inited()
261 	return 0;  in xgene_ahci_read_id()
269 	dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",  in xgene_ahci_set_phy_cfg()
272 	val = PORTADDR_SET(val, channel == 0 ? 2 : 3);  in xgene_ahci_set_phy_cfg()
276 	writel(0x0001fffe, mmio + PORTPHY1CFG);  in xgene_ahci_set_phy_cfg()
278 	writel(0x28183219, mmio + PORTPHY2CFG);  in xgene_ahci_set_phy_cfg()
280 	writel(0x13081008, mmio + PORTPHY3CFG);  in xgene_ahci_set_phy_cfg()
282 	writel(0x00480815, mmio + PORTPHY4CFG);  in xgene_ahci_set_phy_cfg()
286 	val = PORTPHY5CFG_RTCHG_SET(val, 0x300);  in xgene_ahci_set_phy_cfg()
290 	val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */  in xgene_ahci_set_phy_cfg()
291 	val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */  in xgene_ahci_set_phy_cfg()
296 	val = PORTRANSCFG_RXWM_SET(val, 0x30);  in xgene_ahci_set_phy_cfg()
358 	int link_down_retry = 0;  in xgene_ahci_do_hardreset()
366 		ata_tf_to_fis(&tf, 0, 0, d2h_fis);  in xgene_ahci_do_hardreset()
378 		 (sstatus & 0xff) == 0x1);  in xgene_ahci_do_hardreset()
486  *    0xF for both PMP/NON-PMP initially
567 		for (i = 0; i < host->n_ports; i++) {  in xgene_ahci_handle_broken_edge_irq()
584 	unsigned int rc = 0;  in xgene_ahci_irq_intr()
591 	/* sigh.  0xffffffff is a valid return from h/w */  in xgene_ahci_irq_intr()
656 	for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)  in xgene_ahci_hw_init()
660 	writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);  in xgene_ahci_hw_init()
662 	writel(0, ctx->csr_core + INTSTATUSMASK);  in xgene_ahci_hw_init()
664 	dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",  in xgene_ahci_hw_init()
667 	writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);  in xgene_ahci_hw_init()
669 	writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
673 	writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);  in xgene_ahci_hw_init()
674 	writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);  in xgene_ahci_hw_init()
675 	writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);  in xgene_ahci_hw_init()
676 	writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);  in xgene_ahci_hw_init()
680 	val &= ~0x00000002;     /* Enable write coherency */  in xgene_ahci_hw_init()
681 	val &= ~0x00000001;     /* Enable read coherency */  in xgene_ahci_hw_init()
689 	dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",  in xgene_ahci_hw_init()
701 		return 0;  in xgene_ahci_mux_select()
707 	return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;  in xgene_ahci_mux_select()
741 	hpriv = ahci_platform_get_resources(pdev, 0);  in xgene_ahci_probe()
807 	dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,  in xgene_ahci_probe()
853 	return 0;  in xgene_ahci_probe()