drivers/acpi/cppc_acpi.c

26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
28  * See drivers/mailbox/pcc.c for details on PCC.
30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
55 	bool pending_pcc_write_cmd;	/* Any pending/batched PCC write cmds? */
56 	bool platform_owns_pcc;		/* Ownership of PCC subspace */
57 	unsigned int pcc_write_cnt;	/* Running count of PCC write commands */
60 	 * Lock to provide controlled access to the PCC channel.
64 	 * before reading or writing to PCC subspace
83 /* Array to represent the PCC channel per subspace ID */
91  * include the type of register (e.g. PCC, System IO, FFH etc.)
97 /* pcc mapped address + header size + offset within PCC subspace */
101 /* Check if a CPC register is in PCC */
134  * to PCC commands. Keeping it high enough to cover emulators where
232 	 * Poll PCC status register every 3us(delay_us) for maximum of  in check_pcc_chan()
233 	 * deadline_us(timeout_us) until PCC command complete bit is set(cond)  in check_pcc_chan()
246 		pr_err("PCC check channel failed for ss: %d. ret=%d\n",  in check_pcc_chan()
253  * This function transfers the ownership of the PCC to the platform
266 	 * the channel before writing to PCC space  in send_pcc_cmd()
311 				pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",  in send_pcc_cmd()
333 		pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",  in send_pcc_cmd()
338 	/* wait for completion and check for PCC error bit */  in send_pcc_cmd()
557 			pr_err("Failed to find PCC channel for subspace %d\n",  in register_pcc_channel()
578 			pr_err("Failed to ioremap PCC comm region mem for %d\n",  in register_pcc_channel()
617  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
618  * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
651  *      ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)},	// Highest Performance
652  *      ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)},	// Nominal Performance
653  *      ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)},	// Lowest Nonlinear Performance
654  *      ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)},	// Lowest Performance
655  *      ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)},	// Guaranteed Performance Register
656  *      ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)},	// Desired Performance Register
663  * e.g. a sample PCC entry has the following encoding:
666  *      PCC,	// AddressSpaceKeyword
780 			 * The PCC Subspace index is encoded inside  in acpi_cppc_processor_probe()
781 			 * the CPC table entries. The same PCC index  in acpi_cppc_processor_probe()
782 			 * will be used for all the PCC entries,  in acpi_cppc_processor_probe()
791 					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",  in acpi_cppc_processor_probe()
836 					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */  in acpi_cppc_processor_probe()
873 	/* Register PCC channel once for all PCC subspace ID. */  in acpi_cppc_processor_probe()
995  * as fast as possible. We have already mapped the PCC subspace during init, so
1030 		 * For registers in PCC space, the register size is determined  in cpc_read()
1032 		 * the PCC subspace id.  in cpc_read()
1063 			pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",  in cpc_read()
1102 		 * For registers in PCC space, the register size is determined  in cpc_write()
1104 		 * the PCC subspace id.  in cpc_write()
1164 			pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",  in cpc_write()
1298 	/* Are any of the regs PCC ?*/  in cppc_get_perf_caps()
1309 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_caps()
1358  * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1361  * One of the choices is PCC regions, which can have a high access latency. This
1364  * Return: true if any of the counters are in PCC regions, false otherwise
1433 	/* Are any of the regs PCC ?*/  in cppc_get_perf_ctrs()
1443 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_ctrs()
1521 		/* after writing CPC, transfer the ownership of PCC to platform */  in cppc_set_epp_perf()
1529 		pr_debug("_CPC in PCC and _CPC in FFH are not supported\n");  in cppc_set_epp_perf()
1620 		/* after writing CPC, transfer the ownership of PCC to platform */  in cppc_set_auto_sel()
1625 		pr_debug("_CPC in PCC is not supported\n");  in cppc_set_auto_sel()
1667 		/* after writing CPC, transfer the ownership of PCC to platfrom */  in cppc_set_enable()
1723 		 * Update the pending_write to make sure a PCC CMD_READ will not  in cppc_set_perf()
1746 	 * This is Phase-II where we transfer the ownership of PCC to Platform  in cppc_set_perf()
1761 	 * PCC ownership to the platform, then one of the following will be TRUE  in cppc_set_perf()
1769 	 *     3. Some other CPU executing pcc CMD_READ has stolen the  in cppc_set_perf()
1781 	 * doorbell and transferred the ownership of PCC to platform. So this  in cppc_set_perf()
1783 	 * triggering the doorbell it makes sure that the PCC channel ownership  in cppc_set_perf()
1786 	 * there was a pcc CMD_READ waiting on down_write and it steals the lock  in cppc_set_perf()
1787 	 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this  in cppc_set_perf()
1816  * on the number and frequency of PCC commands the platform can handle.