accel/qaic/qaic.h

1 /* SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
25 #define QAIC_NO_PARTITION	-1
31 #define to_drm(qddev) (&(qddev)->drm)
32 #define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */
33 #define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev)
62 	/* ID of this DMA bridge channel(DBC) */
130 	/* Work queue for tasks related to MHI control device */
154 	/* Work queue for tasks related to MHI "QAIC_TIMESYNC" channel */
160 	/* Work queue for tasks related to MHI bootlog device */
201 	/* Number of slice that have been transferred by DMA engine */
212 	/* Wait on this for completion of DMA transfer of this BO */
215 	 * Node in linked list where head is dbc->xfer_list.
216 	 * This link list contain BO's that are queued for DMA transfer.
220 	 * Node in linked list where head is dbc->bo_lists.
233 		 * this BO for execution in DMA queue
242 		 * Number of elements already enqueued in DMA queue before
254 	/* Number of requests required to queue in DMA queue */
258 	/* Actual requests that will be copied in DMA queue */
261 	/* true: No DMA transfer required */