Lines Matching +full:level +full:- +full:detect
1 /* SPDX-License-Identifier: MIT */
3 * Copyright (c) 2020-2023, Intel Corporation.
12 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
42 /* ------------ FW API version information end ---------------------*/
70 * Size of primary preemption buffer, assuming a 2-job submission queue.
76 * Size of secondary preemption buffer, assuming a 2-job submission queue.
81 /* Space reserved for future preemption-related fields. */
207 /* Clock frequencies: 0x20 - 0xFF */
212 /* Memory regions: 0x100 - 0x1FF */
232 /* IRQ re-direct numbers: 0x200 - 0x2FF */
235 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
237 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
239 /* VPU -> ARM IRQ line to use to request MMU update. */
241 /* ARM -> VPU IRQ line to use to notify of MMU update completion. */
243 /* ARM -> VPU IRQ line to use to request power level change. */
245 /* VPU -> ARM IRQ line to use to notify of power level change completion. */
247 /* VPU -> ARM IRQ line to use to notify of VPU idle state change */
249 /* VPU -> ARM IRQ line to use to request counter reset. */
251 /* ARM -> VPU IRQ line to use to notify of counter reset completion. */
253 /* VPU -> ARM IRQ line to use to notify of preemption completion. */
257 /* Silicon information: 0x300 - 0x3FF */
268 * Initial log level threshold (messages with log level severity less than
272 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
308 * On-demand: Default if 0.
309 * Bit 0-7 - uint8_t: Highest residency percent
310 * Bit 8-15 - uint8_t: High residency percent
311 * Bit 16-23 - uint8_t: Low residency percent
312 * Bit 24-31 - uint8_t: Lowest residency percent
313 * Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
314 * Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
315 * Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
316 * Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
317 * Bit 48-55 - uint8_t: Period (ms) for residency decisions
318 * Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
349 /* Warm boot information: 0x400 - 0x43F */
354 /* Power States transitions timestamps: 0x440 - 0x46F*/
356 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
358 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
360 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
362 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
364 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
366 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
381 /* Unused/reserved: 0x488 - 0xFFF */
386 * Magic numbers set between host and vpu to detect corruptio of tracing init
402 * Magic number set by host to detect corruption
412 * Magic number set by host to detect corruption
420 /* legacy field - do not use */
434 * 0 - null terminated string
435 * 1 - size + null terminated string
436 * 2 - MIPI-SysT encoding
441 * 0 - messages are place 1 after another
442 * n - every message starts and multiple on offset