Lines Matching full:reg
18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) argument
19 #define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg)) argument
20 #define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__) argument
21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) argument
25 #define REGV_RD32_SILENT(reg) readl(vdev->regv + (reg)) argument
26 #define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__) argument
27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
30 #define REGV_WR32I(reg, stride, index, val) \ argument
31 ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
33 #define REG_FLD(REG, FLD) \ argument
34 (REG##_##FLD##_MASK)
35 #define REG_FLD_NUM(REG, FLD, num) \ argument
36 FIELD_PREP(REG##_##FLD##_MASK, num)
37 #define REG_GET_FLD(REG, FLD, val) \ argument
38 FIELD_GET(REG##_##FLD##_MASK, val)
39 #define REG_CLR_FLD(REG, FLD, val) \ argument
40 ((val) & ~(REG##_##FLD##_MASK))
41 #define REG_SET_FLD(REG, FLD, val) \ argument
42 ((val) | (REG##_##FLD##_MASK))
43 #define REG_SET_FLD_NUM(REG, FLD, num, val) \ argument
44 (((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
45 #define REG_TEST_FLD(REG, FLD, val) \ argument
46 ((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
47 #define REG_TEST_FLD_NUM(REG, FLD, num, val) \ argument
48 ((num) == FIELD_GET(REG##_##FLD##_MASK, val))
50 #define REGB_POLL_FLD(reg, fld, val, timeout_us) \ argument
54 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s started (expected 0x%x)\n", \
55 __func__, #reg, reg, #fld, val); \
56 r = read_poll_timeout(REGB_RD32_SILENT, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)),\
57 REG_POLL_SLEEP_US, timeout_us, false, (reg)); \
58 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s %s (reg val 0x%08x)\n", \
59 __func__, #reg, reg, #fld, r ? "ETIMEDOUT" : "OK", var); \
63 #define REGV_POLL_FLD(reg, fld, val, timeout_us) \ argument
67 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s started (expected 0x%x)\n", \
68 __func__, #reg, reg, #fld, val); \
69 r = read_poll_timeout(REGV_RD32_SILENT, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)),\
70 REG_POLL_SLEEP_US, timeout_us, false, (reg)); \
71 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s %s (reg val 0x%08x)\n", \
72 __func__, #reg, reg, #fld, r ? "ETIMEDOUT" : "OK", var); \
77 ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg, in ivpu_hw_reg_rd32() argument
80 u32 val = readl(base + reg); in ivpu_hw_reg_rd32()
82 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_rd32()
87 ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg, in ivpu_hw_reg_rd64() argument
90 u64 val = readq(base + reg); in ivpu_hw_reg_rd64()
92 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_rd64()
97 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val, in ivpu_hw_reg_wr32() argument
100 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_wr32()
101 writel(val, base + reg); in ivpu_hw_reg_wr32()
105 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val, in ivpu_hw_reg_wr64() argument
108 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_wr64()
109 writeq(val, base + reg); in ivpu_hw_reg_wr64()
113 ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg, in ivpu_hw_reg_wr32_index() argument
117 reg += index * stride; in ivpu_hw_reg_wr32_index()
119 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val); in ivpu_hw_reg_wr32_index()
120 writel(val, base + reg); in ivpu_hw_reg_wr32_index()