139 		ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);  in read_tile_config_fuse()
145 		ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", config);  in read_tile_config_fuse()
287 		ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);  in wp_request_send()
295 		ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);  in wp_request_send()
354 		ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret);  in ivpu_hw_btrs_wp_drive()
360 		ivpu_err(vdev, "Timed out waiting for PLL lock\n");  in ivpu_hw_btrs_wp_drive()
366 		ivpu_err(vdev, "Timed out waiting for NPU ready status\n");  in ivpu_hw_btrs_wp_drive()
380 		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);  in d0i3_drive_mtl()
393 		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);  in d0i3_drive_mtl()
405 		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);  in d0i3_drive_lnl()
418 		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);  in d0i3_drive_lnl()
442 		ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_enable()
458 		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_disable()
487 		ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");  in ip_reset_mtl()
497 		ivpu_err(vdev, "Timed out waiting for RESET completion\n");  in ip_reset_mtl()
511 		ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");  in ip_reset_lnl()
521 		ivpu_err(vdev, "Timed out waiting for RESET completion\n");  in ip_reset_lnl()
605 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));  in ivpu_hw_btrs_irq_handler_mtl()
613 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",  in ivpu_hw_btrs_irq_handler_mtl()
656 		ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",  in ivpu_hw_btrs_irq_handler_lnl()
664 		ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));  in ivpu_hw_btrs_irq_handler_lnl()
670 		ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));  in ivpu_hw_btrs_irq_handler_lnl()
676 		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",  in ivpu_hw_btrs_irq_handler_lnl()
684 		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",  in ivpu_hw_btrs_irq_handler_lnl()
857 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));  in diagnose_failure_mtl()
862 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",  in diagnose_failure_mtl()
874 		ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",  in diagnose_failure_lnl()
880 		ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));  in diagnose_failure_lnl()
883 		ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));  in diagnose_failure_lnl()
886 		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",  in diagnose_failure_lnl()
891 		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",  in diagnose_failure_lnl()
896 		ivpu_err(vdev, "Survivability IRQ\n");  in diagnose_failure_lnl()