67 	REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK);  in ivpu_hw_btrs_irqs_clear_with_0_mtl()
70 		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);  in ivpu_hw_btrs_irqs_clear_with_0_mtl()
233 	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val);  in wp_request_mtl()
238 	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val);  in wp_request_mtl()
242 	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val);  in wp_request_mtl()
246 	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val);  in wp_request_mtl()
256 	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val);  in wp_request_lnl()
261 	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val);  in wp_request_lnl()
266 	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val);  in wp_request_lnl()
270 	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val);  in wp_request_lnl()
389 	REGB_WR32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, val);  in d0i3_drive_mtl()
414 	REGB_WR32(VPU_HW_BTRS_LNL_D0I3_CONTROL, val);  in d0i3_drive_lnl()
476 	REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);  in ivpu_hw_btrs_set_port_arbitration_weights_lnl()
477 	REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);  in ivpu_hw_btrs_set_port_arbitration_weights_lnl()
493 	REGB_WR32(VPU_HW_BTRS_MTL_VPU_IP_RESET, val);  in ip_reset_mtl()
517 	REGB_WR32(VPU_HW_BTRS_LNL_IP_RESET, val);  in ip_reset_lnl()
546 	REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);  in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
560 	REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);  in ivpu_hw_btrs_clock_relinquish_disable_lnl()
606 		REGB_WR32(VPU_HW_BTRS_MTL_ATS_ERR_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_mtl()
617 		REGB_WR32(VPU_HW_BTRS_MTL_UFI_ERR_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_mtl()
627 		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);  in ivpu_hw_btrs_irq_handler_mtl()
629 		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status);  in ivpu_hw_btrs_irq_handler_mtl()
659 		REGB_WR32(VPU_HW_BTRS_LNL_ATS_ERR_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_lnl()
665 		REGB_WR32(VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_lnl()
671 		REGB_WR32(VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_lnl()
679 		REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_lnl()
687 		REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR, 0x1);  in ivpu_hw_btrs_irq_handler_lnl()
692 	REGB_WR32(VPU_HW_BTRS_LNL_INTERRUPT_STAT, status);  in ivpu_hw_btrs_irq_handler_lnl()
733 	REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val);  in ivpu_hw_btrs_dct_set_status()
817 		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_btrs_global_int_disable()
819 		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_btrs_global_int_disable()
825 		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_btrs_global_int_enable()
827 		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_btrs_global_int_enable()
833 		REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~BTRS_MTL_IRQ_MASK));  in ivpu_hw_btrs_irq_enable()
834 		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_btrs_irq_enable()
836 		REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~BTRS_LNL_IRQ_MASK));  in ivpu_hw_btrs_irq_enable()
837 		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);  in ivpu_hw_btrs_irq_enable()
844 		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_btrs_irq_disable()
845 		REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);  in ivpu_hw_btrs_irq_disable()
847 		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);  in ivpu_hw_btrs_irq_disable()
848 		REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);  in ivpu_hw_btrs_irq_disable()