1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2020-2024 Intel Corporation
27 #define BTRS_IRQ_DISABLE_MASK ((u32)-1)
29 #define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
79 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_mtl()
83 	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);  in freq_ratios_init_mtl()
84 	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);  in freq_ratios_init_mtl()
87 	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);  in freq_ratios_init_mtl()
92 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_lnl()
96 	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);  in freq_ratios_init_lnl()
97 	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);  in freq_ratios_init_lnl()
100 	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);  in freq_ratios_init_lnl()
105 	struct ivpu_hw_info *hw = vdev->hw;  in ivpu_hw_btrs_freq_ratios_init()
112 	hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
113 	hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
114 	hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
119 	/* Allowed values: 0 or one bit from range 0-5 (6 tiles) */  in tile_disable_check()
123 	if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))  in tile_disable_check()
126 	if ((config & (config - 1)) == 0)  in tile_disable_check()
140 		return -EIO;  in read_tile_config_fuse()
145 		ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", config);  in read_tile_config_fuse()
146 		return -EIO;  in read_tile_config_fuse()
151 			 BTRS_LNL_TILE_MAX_NUM - 1, ffs(config) - 1);  in read_tile_config_fuse()
161 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_mtl()
163 	hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;  in info_init_mtl()
164 	hw->sku = BTRS_MTL_TILE_SKU_BOTH;  in info_init_mtl()
165 	hw->config = BTRS_MTL_WP_CONFIG_2_TILE_4_3_RATIO;  in info_init_mtl()
166 	hw->sched_mode = ivpu_sched_mode;  in info_init_mtl()
173 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_lnl()
181 	hw->sched_mode = ivpu_sched_mode;  in info_init_lnl()
182 	hw->tile_fuse = tile_fuse_config;  in info_init_lnl()
183 	hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;  in info_init_lnl()
226 static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_mtl()  argument
231 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);  in wp_request_mtl()
232 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);  in wp_request_mtl()
236 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);  in wp_request_mtl()
241 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);  in wp_request_mtl()
249 static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_lnl()  argument
254 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);  in wp_request_lnl()
255 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);  in wp_request_lnl()
259 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);  in wp_request_lnl()
260 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);  in wp_request_lnl()
264 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);  in wp_request_lnl()
265 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);  in wp_request_lnl()
273 static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request()  argument
276 		wp_request_mtl(vdev, wp);  in wp_request()
278 		wp_request_lnl(vdev, wp);  in wp_request()
281 static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_send()  argument
291 	wp_request(vdev, wp);  in wp_request_send()
300 static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)  in prepare_wp_request()  argument
302 	struct ivpu_hw_info *hw = vdev->hw;  in prepare_wp_request()
304 	wp->min = hw->pll.min_ratio;  in prepare_wp_request()
305 	wp->max = hw->pll.max_ratio;  in prepare_wp_request()
308 		wp->target = enable ? hw->pll.pn_ratio : 0;  in prepare_wp_request()
309 		wp->cfg = enable ? hw->config : 0;  in prepare_wp_request()
310 		wp->cdyn = 0;  in prepare_wp_request()
311 		wp->epp = 0;  in prepare_wp_request()
313 		wp->target = hw->pll.pn_ratio;  in prepare_wp_request()
314 		wp->cfg = enable ? PLL_CONFIG_DEFAULT : 0;  in prepare_wp_request()
315 		wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;  in prepare_wp_request()
316 		wp->epp = enable ? PLL_EPP_DEFAULT : 0;  in prepare_wp_request()
321 		wp->cfg = 1;  in prepare_wp_request()
339 	struct wp_request wp;  in ivpu_hw_btrs_wp_drive()  local
347 	prepare_wp_request(vdev, &wp, enable);  in ivpu_hw_btrs_wp_drive()
350 		 PLL_RATIO_TO_FREQ(wp.target), wp.cfg, wp.epp, wp.cdyn);  in ivpu_hw_btrs_wp_drive()
352 	ret = wp_request_send(vdev, &wp);  in ivpu_hw_btrs_wp_drive()
458 		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_disable()
541 	if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)  in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
552 		 REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable");  in ivpu_hw_btrs_ats_print_lnl()
648 		if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_DCT))  in ivpu_hw_btrs_irq_handler_lnl()
708 		return -EBADR;  in ivpu_hw_btrs_dct_get_request()
720 		return -EINVAL;  in ivpu_hw_btrs_dct_get_request()
751 	struct ivpu_hw_info *hw = vdev->hw;  in ivpu_hw_btrs_ratio_to_freq()
754 		return pll_ratio_to_freq_mtl(ratio, hw->config);  in ivpu_hw_btrs_ratio_to_freq()
769 	return pll_ratio_to_freq_mtl(pll_curr_ratio, vdev->hw->config);  in pll_freq_get_mtl()