Lines Matching +full:0 +full:x3ffff
23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
43 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0
44 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1
46 #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2
48 #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4
50 #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8
52 #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10
54 #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20
56 #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40
58 #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100
60 #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200
62 #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400
64 #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800
66 #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000
68 #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000
70 #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000
73 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
74 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
76 #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
78 #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
80 #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
82 #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10
84 #define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20
87 #define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0
88 #define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF
91 #define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0
92 #define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF
95 #define MMU_LOG2_DDR_SIZE_R_SHIFT 0
96 #define MMU_LOG2_DDR_SIZE_R_MASK 0xFF
99 #define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0
100 #define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F
102 #define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40
104 #define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80
107 #define MMU_MEM_INIT_BUSY_DATA_SHIFT 0
108 #define MMU_MEM_INIT_BUSY_DATA_MASK 0x3
110 #define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4
112 #define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8
115 #define MMU_SPI_MASK_R_SHIFT 0
116 #define MMU_SPI_MASK_R_MASK 0xFF
119 #define MMU_SPI_CAUSE_R_SHIFT 0
120 #define MMU_SPI_CAUSE_R_MASK 0xFF
123 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0
124 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
126 #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
129 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
130 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
133 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0
134 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
136 #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
139 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
140 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF