Lines Matching +full:16 +full:mb

16 #define CFG_BAR_SIZE		0x10000000ull		/* 256MB */
18 #define MSIX_BAR_SIZE		0x4000ull		/* 16KB */
21 #define CFG_SIZE		0x8000000ull		/* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE		0xC000000ull		/* 192MB */
24 #define STM_FLASH_BASE_ADDR	0x1000007FF4000000ull	/* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF	0x4000000ull		/* 256 MB alignment */
26 #define STM_FLASH_SIZE		0x2000000ull		/* 32MB */
29 #define SPI_FLASH_SIZE		0x1000000ull		/* 16MB */
38 #define BAR0_RSRVD_SIZE		0x1000000ull		/* 16MB */
41 #define SRAM_SIZE		0x3000000ull		/* 48MB */
70 #define QMAN_PQ_ENTRY_SIZE	16			/* Bytes */
110 #define TPC_NUM_OF_KERNEL_TENSORS	16
111 #define TPC_NUM_OF_QM_TENSORS		16