18 #define SPMU_EVENT_TYPES_OFFSET		0x400
220 			"Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",  in goya_coresight_timeout()
225 	return 0;  in goya_coresight_timeout()
243 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);  in goya_config_stm()
251 		WREG32(base_reg + 0xE80, 0x80004);  in goya_config_stm()
252 		WREG32(base_reg + 0xD64, 7);  in goya_config_stm()
253 		WREG32(base_reg + 0xD60, 0);  in goya_config_stm()
254 		WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));  in goya_config_stm()
255 		WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));  in goya_config_stm()
256 		WREG32(base_reg + 0xD60, 1);  in goya_config_stm()
257 		WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));  in goya_config_stm()
258 		WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));  in goya_config_stm()
259 		WREG32(base_reg + 0xE70, 0x10);  in goya_config_stm()
260 		WREG32(base_reg + 0xE60, 0);  in goya_config_stm()
261 		WREG32(base_reg + 0xE64, 0x420000);  in goya_config_stm()
262 		WREG32(base_reg + 0xE00, 0xFFFFFFFF);  in goya_config_stm()
263 		WREG32(base_reg + 0xE20, 0xFFFFFFFF);  in goya_config_stm()
264 		WREG32(base_reg + 0xEF4, input->id);  in goya_config_stm()
265 		WREG32(base_reg + 0xDF4, 0x80);  in goya_config_stm()
267 		if (frequency == 0)  in goya_config_stm()
269 		WREG32(base_reg + 0xE8C, frequency);  in goya_config_stm()
270 		WREG32(base_reg + 0xE90, 0x7FF);  in goya_config_stm()
271 		WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));  in goya_config_stm()
273 		WREG32(base_reg + 0xE80, 4);  in goya_config_stm()
274 		WREG32(base_reg + 0xD64, 0);  in goya_config_stm()
275 		WREG32(base_reg + 0xD60, 1);  in goya_config_stm()
276 		WREG32(base_reg + 0xD00, 0);  in goya_config_stm()
277 		WREG32(base_reg + 0xD20, 0);  in goya_config_stm()
278 		WREG32(base_reg + 0xD60, 0);  in goya_config_stm()
279 		WREG32(base_reg + 0xE20, 0);  in goya_config_stm()
280 		WREG32(base_reg + 0xE00, 0);  in goya_config_stm()
281 		WREG32(base_reg + 0xDF4, 0x80);  in goya_config_stm()
282 		WREG32(base_reg + 0xE70, 0);  in goya_config_stm()
283 		WREG32(base_reg + 0xE60, 0);  in goya_config_stm()
284 		WREG32(base_reg + 0xE64, 0);  in goya_config_stm()
285 		WREG32(base_reg + 0xE8C, 0);  in goya_config_stm()
287 		rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);  in goya_config_stm()
295 		WREG32(base_reg + 0xE80, 4);  in goya_config_stm()
298 	return 0;  in goya_config_stm()
316 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);  in goya_config_etf()
318 	val = RREG32(base_reg + 0x20);  in goya_config_etf()
320 	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))  in goya_config_etf()
321 		return 0;  in goya_config_etf()
323 	val = RREG32(base_reg + 0x304);  in goya_config_etf()
324 	val |= 0x1000;  in goya_config_etf()
325 	WREG32(base_reg + 0x304, val);  in goya_config_etf()
326 	val |= 0x40;  in goya_config_etf()
327 	WREG32(base_reg + 0x304, val);  in goya_config_etf()
329 	rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);  in goya_config_etf()
337 	rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);  in goya_config_etf()
345 	WREG32(base_reg + 0x20, 0);  in goya_config_etf()
353 		WREG32(base_reg + 0x34, 0x3FFC);  in goya_config_etf()
354 		WREG32(base_reg + 0x28, input->sink_mode);  in goya_config_etf()
355 		WREG32(base_reg + 0x304, 0x4001);  in goya_config_etf()
356 		WREG32(base_reg + 0x308, 0xA);  in goya_config_etf()
357 		WREG32(base_reg + 0x20, 1);  in goya_config_etf()
359 		WREG32(base_reg + 0x34, 0);  in goya_config_etf()
360 		WREG32(base_reg + 0x28, 0);  in goya_config_etf()
361 		WREG32(base_reg + 0x304, 0);  in goya_config_etf()
364 	return 0;  in goya_config_etf()
396 	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))  in goya_config_etr()
397 		return 0;  in goya_config_etr()
400 	val |= 0x1000;  in goya_config_etr()
402 	val |= 0x40;  in goya_config_etr()
419 	WREG32(mmPSOC_ETR_CTL, 0);  in goya_config_etr()
427 		if (input->buffer_size == 0) {  in goya_config_etr()
429 				"ETR buffer size should be bigger than 0\n");  in goya_config_etr()
439 		WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);  in goya_config_etr()
444 			val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);  in goya_config_etr()
456 		WREG32(mmPSOC_ETR_PSCR, 0xA);  in goya_config_etr()
459 		WREG32(mmPSOC_ETR_BUFWM, 0);  in goya_config_etr()
460 		WREG32(mmPSOC_ETR_RSZ, 0x400);  in goya_config_etr()
461 		WREG32(mmPSOC_ETR_DBALO, 0);  in goya_config_etr()
462 		WREG32(mmPSOC_ETR_DBAHI, 0);  in goya_config_etr()
463 		WREG32(mmPSOC_ETR_PSCR, 0);  in goya_config_etr()
464 		WREG32(mmPSOC_ETR_MODE, 0);  in goya_config_etr()
465 		WREG32(mmPSOC_ETR_FFCR, 0);  in goya_config_etr()
476 			rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;  in goya_config_etr()
481 	return 0;  in goya_config_etr()
496 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);  in goya_config_funnel()
498 	WREG32(base_reg, params->enable ? 0x33F : 0);  in goya_config_funnel()
500 	return 0;  in goya_config_funnel()
508 	u32 pcie_base = 0;  in goya_config_bmon()
517 	WREG32(base_reg + 0x104, 1);  in goya_config_bmon()
525 		WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));  in goya_config_bmon()
526 		WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));  in goya_config_bmon()
527 		WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));  in goya_config_bmon()
528 		WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));  in goya_config_bmon()
529 		WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));  in goya_config_bmon()
530 		WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));  in goya_config_bmon()
531 		WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));  in goya_config_bmon()
532 		WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));  in goya_config_bmon()
533 		WREG32(base_reg + 0x224, 0);  in goya_config_bmon()
534 		WREG32(base_reg + 0x234, 0);  in goya_config_bmon()
535 		WREG32(base_reg + 0x30C, input->bw_win);  in goya_config_bmon()
536 		WREG32(base_reg + 0x308, input->win_capture);  in goya_config_bmon()
543 			pcie_base = 0xA000000;  in goya_config_bmon()
545 		WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));  in goya_config_bmon()
546 		WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));  in goya_config_bmon()
547 		WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));  in goya_config_bmon()
549 		WREG32(base_reg + 0x100, 0x11);  in goya_config_bmon()
550 		WREG32(base_reg + 0x304, 0x1);  in goya_config_bmon()
552 		WREG32(base_reg + 0x200, 0);  in goya_config_bmon()
553 		WREG32(base_reg + 0x204, 0);  in goya_config_bmon()
554 		WREG32(base_reg + 0x208, 0xFFFFFFFF);  in goya_config_bmon()
555 		WREG32(base_reg + 0x20C, 0xFFFFFFFF);  in goya_config_bmon()
556 		WREG32(base_reg + 0x240, 0);  in goya_config_bmon()
557 		WREG32(base_reg + 0x244, 0);  in goya_config_bmon()
558 		WREG32(base_reg + 0x248, 0xFFFFFFFF);  in goya_config_bmon()
559 		WREG32(base_reg + 0x24C, 0xFFFFFFFF);  in goya_config_bmon()
560 		WREG32(base_reg + 0x224, 0xFFFFFFFF);  in goya_config_bmon()
561 		WREG32(base_reg + 0x234, 0x1070F);  in goya_config_bmon()
562 		WREG32(base_reg + 0x30C, 0);  in goya_config_bmon()
563 		WREG32(base_reg + 0x308, 0xFFFF);  in goya_config_bmon()
564 		WREG32(base_reg + 0x700, 0xA000B00);  in goya_config_bmon()
565 		WREG32(base_reg + 0x708, 0xA000A00);  in goya_config_bmon()
566 		WREG32(base_reg + 0x70C, 0xA000C00);  in goya_config_bmon()
567 		WREG32(base_reg + 0x100, 1);  in goya_config_bmon()
568 		WREG32(base_reg + 0x304, 0);  in goya_config_bmon()
569 		WREG32(base_reg + 0x104, 0);  in goya_config_bmon()
572 	return 0;  in goya_config_bmon()
611 		WREG32(base_reg + 0xE04, 0x41013046);  in goya_config_spmu()
612 		WREG32(base_reg + 0xE04, 0x41013040);  in goya_config_spmu()
614 		for (i = 0 ; i < input->event_types_num ; i++)  in goya_config_spmu()
618 		WREG32(base_reg + 0xE04, 0x41013041);  in goya_config_spmu()
619 		WREG32(base_reg + 0xC00, 0x8000003F);  in goya_config_spmu()
642 		WREG32(base_reg + 0xE04, 0x41013040);  in goya_config_spmu()
644 		for (i = 0 ; i < events_num ; i++)  in goya_config_spmu()
647 		output[overflow_idx] = RREG32(base_reg + 0xCC0);  in goya_config_spmu()
649 		output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);  in goya_config_spmu()
651 		output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);  in goya_config_spmu()
653 		WREG32(base_reg + 0xCC0, 0);  in goya_config_spmu()
656 	return 0;  in goya_config_spmu()
662 	int rc = 0;  in goya_debug_coresight()