2991 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;  in gaudi2_write_hbw_range_register()  local
2998 		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;  in gaudi2_write_hbw_range_register()
3005 		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;  in gaudi2_write_hbw_range_register()
3012 		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;  in gaudi2_write_hbw_range_register()
3019 		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;  in gaudi2_write_hbw_range_register()
3030 	min_hi_reg_offset += rr_cfg->index * sizeof(u32);  in gaudi2_write_hbw_range_register()
3051 	WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));  in gaudi2_write_hbw_range_register()
3136 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;  in gaudi2_write_mmu_range_register()  local
3141 		min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;  in gaudi2_write_mmu_range_register()
3148 		min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;  in gaudi2_write_mmu_range_register()
3159 	min_hi_reg_offset += rr_cfg->index * sizeof(u32);  in gaudi2_write_mmu_range_register()
3165 	WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));  in gaudi2_write_mmu_range_register()