Lines Matching refs:max_lo_reg_offset
2991 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; in gaudi2_write_hbw_range_register() local
2999 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET; in gaudi2_write_hbw_range_register()
3006 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET; in gaudi2_write_hbw_range_register()
3013 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET; in gaudi2_write_hbw_range_register()
3020 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET; in gaudi2_write_hbw_range_register()
3031 max_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_hbw_range_register()
3052 WREG32(base + max_lo_reg_offset, lower_32_bits(val_max)); in gaudi2_write_hbw_range_register()
3136 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; in gaudi2_write_mmu_range_register() local
3142 max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET; in gaudi2_write_mmu_range_register()
3149 max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET; in gaudi2_write_mmu_range_register()
3160 max_lo_reg_offset += rr_cfg->index * sizeof(u32); in gaudi2_write_mmu_range_register()
3166 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max)); in gaudi2_write_mmu_range_register()