3226 	u32 instance_offset;  in gaudi2_init_protection_bits()  local
3231 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;  in gaudi2_init_protection_bits()
3232 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_init_protection_bits()
3237 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;  in gaudi2_init_protection_bits()
3239 			NUM_OF_HIF_PER_DCORE, instance_offset,  in gaudi2_init_protection_bits()
3244 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;  in gaudi2_init_protection_bits()
3245 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_init_protection_bits()
3277 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;  in gaudi2_init_protection_bits()
3278 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_init_protection_bits()
3285 			instance_offset, gaudi2_pb_pdma0_arc,  in gaudi2_init_protection_bits()
3291 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;  in gaudi2_init_protection_bits()
3293 			instance_offset, gaudi2_pb_dcr0_edma0,  in gaudi2_init_protection_bits()
3301 			instance_offset, gaudi2_pb_dcr0_edma0_arc,  in gaudi2_init_protection_bits()
3308 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;  in gaudi2_init_protection_bits()
3313 				instance_offset, gaudi2_pb_dcr0_mme_sbte,  in gaudi2_init_protection_bits()
3362 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;  in gaudi2_init_protection_bits()
3363 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_init_protection_bits()
3461 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;  in gaudi2_init_protection_bits()
3462 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_init_protection_bits()
3468 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;  in gaudi2_init_protection_bits()
3471 			instance_offset, gaudi2_pb_arc_sched,  in gaudi2_init_protection_bits()
3477 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;  in gaudi2_init_protection_bits()
3479 			instance_offset, gaudi2_pb_xbar_mid,  in gaudi2_init_protection_bits()
3485 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;  in gaudi2_init_protection_bits()
3487 			instance_offset, gaudi2_pb_xbar_edge,  in gaudi2_init_protection_bits()
3526 	instance_offset = mmROT1_BASE - mmROT0_BASE;  in gaudi2_init_protection_bits()
3528 			instance_offset, gaudi2_pb_rot0,  in gaudi2_init_protection_bits()
3536 			HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_init_protection_bits()
3613 	u32 instance_offset;  in gaudi2_ack_protection_bits_errors()  local
3617 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;  in gaudi2_ack_protection_bits_errors()
3618 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_ack_protection_bits_errors()
3622 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;  in gaudi2_ack_protection_bits_errors()
3624 			NUM_OF_HIF_PER_DCORE, instance_offset,  in gaudi2_ack_protection_bits_errors()
3629 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;  in gaudi2_ack_protection_bits_errors()
3630 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_ack_protection_bits_errors()
3654 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;  in gaudi2_ack_protection_bits_errors()
3655 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_ack_protection_bits_errors()
3659 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,  in gaudi2_ack_protection_bits_errors()
3663 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;  in gaudi2_ack_protection_bits_errors()
3665 			instance_offset, gaudi2_pb_dcr0_edma0,  in gaudi2_ack_protection_bits_errors()
3671 			instance_offset, gaudi2_pb_dcr0_edma0_arc,  in gaudi2_ack_protection_bits_errors()
3676 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;  in gaudi2_ack_protection_bits_errors()
3681 				instance_offset, gaudi2_pb_dcr0_mme_sbte,  in gaudi2_ack_protection_bits_errors()
3720 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;  in gaudi2_ack_protection_bits_errors()
3721 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,  in gaudi2_ack_protection_bits_errors()
3772 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;  in gaudi2_ack_protection_bits_errors()
3773 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,  in gaudi2_ack_protection_bits_errors()
3778 	instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;  in gaudi2_ack_protection_bits_errors()
3780 			instance_offset, gaudi2_pb_hbm,  in gaudi2_ack_protection_bits_errors()
3784 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;  in gaudi2_ack_protection_bits_errors()
3786 			instance_offset, gaudi2_pb_arc_sched,  in gaudi2_ack_protection_bits_errors()
3790 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;  in gaudi2_ack_protection_bits_errors()
3792 			instance_offset, gaudi2_pb_xbar_mid,  in gaudi2_ack_protection_bits_errors()
3796 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;  in gaudi2_ack_protection_bits_errors()
3798 			instance_offset, gaudi2_pb_xbar_edge,  in gaudi2_ack_protection_bits_errors()
3821 	instance_offset = mmROT1_BASE - mmROT0_BASE;  in gaudi2_ack_protection_bits_errors()
3822 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_ack_protection_bits_errors()
3826 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,  in gaudi2_ack_protection_bits_errors()