1936 const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
1995 static const u32 gaudi2_tpc_initiator_hbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
2003 static const u32 gaudi2_tpc_initiator_lbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
2031 static const u32 gaudi2_edma_initiator_hbw_sft[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
2084 gaudi2_mme_initiator_rtr_id[NUM_OF_MME_PER_DCORE * NUM_OF_DCORES] = {
2244 	for (dcore = 0; dcore < NUM_OF_DCORES; dcore++) {  in gaudi2_iterate_tpcs()
3429 	for (i = 1; i < NUM_OF_DCORES; ++i) {  in gaudi2_user_mapped_blocks_init()
3919 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_stop_dma_qmans()
3943 	for (i = 0 ; i < NUM_OF_DCORES ; i++) {  in gaudi2_stop_mme_qmans()
4030 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_dma_stall()
4054 	for (i = 0 ; i < NUM_OF_DCORES ; i++)  in gaudi2_mme_stall()
4118 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_disable_dma_qmans()
4142 	for (i = 0 ; i < NUM_OF_DCORES ; i++)  in gaudi2_disable_mme_qmans()
4583 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_stop_dec()
5283 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_init_edma()
5505 	for (i = 0 ; i < NUM_OF_DCORES ; i++) {  in gaudi2_init_mme()
5523 	enum gaudi2_queue_id dcore_tpc_qid_base[NUM_OF_DCORES];
5538 		seq = NUM_OF_DCORES * NUM_OF_TPC_PER_DCORE;  in gaudi2_init_tpc_config()
5613 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_init_dec()
5817 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_hmmus_invalidate_cache()
5827 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_hmmus_invalidate_cache()
6102 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)  in gaudi2_hbm_mmu_init()
7156 	for (i = 0; i < NUM_OF_DCORES; i++) {  in gaudi2_get_edma_idle_status()
7291 	for (i = 0 ; i < NUM_OF_DCORES ; i++) {  in gaudi2_get_mme_idle_status()
7398 	for (i = 0 ; i < NUM_OF_DCORES ; i++) {  in gaudi2_get_decoder_idle_status()
7767 	if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 0))  in gaudi2_mmu_shared_prepare()
7770 	if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 1))  in gaudi2_mmu_shared_prepare()
7822 	for (i = 0 ; i < NUM_OF_DCORES ; i++)  in gaudi2_mmu_prepare()
8060 		if (module_idx == (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES))  in gaudi2_razwi_calc_engine_id()
8267 	for (mod_idx = 0 ; mod_idx < (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1) ; mod_idx++) {  in gaudi2_check_if_razwi_happened()
8273 	for (mod_idx = 0 ; mod_idx < (NUM_OF_MME_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)  in gaudi2_check_if_razwi_happened()
8279 	for (mod_idx = 0 ; mod_idx < (NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)  in gaudi2_check_if_razwi_happened()
8758 	if (dec_index < NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES)  in gaudi2_handle_dec_err()
8766 				(dec_index - NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES);  in gaudi2_handle_dec_err()
10357 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_memset_device_memory()
10381 		for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_memset_device_memory()
10414 	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {  in gaudi2_memset_device_memory()
10522 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
10553 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
10572 	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {  in gaudi2_restore_user_sm_registers()
11366 	u32 i, mmu_id, num_of_hmmus = NUM_OF_HMMU_PER_DCORE * NUM_OF_DCORES;  in gaudi2_ack_mmu_page_fault_or_access_error()