2251 			offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst);  in gaudi2_iterate_tpcs()
3434 						mmDCORE0_SYNC_MNGR_OBJS_BASE + i * DCORE_OFFSET;  in gaudi2_user_mapped_blocks_init()
3437 						mmDCORE0_SYNC_MNGR_GLBL_BASE + i * DCORE_OFFSET;  in gaudi2_user_mapped_blocks_init()
3927 			qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +  in gaudi2_stop_dma_qmans()
4038 			core_base = mmDCORE0_EDMA0_CORE_BASE + dcore * DCORE_OFFSET +  in gaudi2_dma_stall()
4126 			qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +  in gaudi2_disable_dma_qmans()
4512 		offset = dcore_id * DCORE_OFFSET + dec_id * DCORE_VDEC_OFFSET;  in gaudi2_stop_dcore_dec()
5622 					dcore_id * DCORE_OFFSET +  in gaudi2_init_dec()
5754 	offset =  (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);  in get_hmmu_stlb_base()
6065 	offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);  in gaudi2_dcore_hmmu_init()
7165 			offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET;  in gaudi2_get_edma_idle_status()
7293 		offset = i * DCORE_OFFSET;  in gaudi2_get_mme_idle_status()
7406 			offset = i * DCORE_OFFSET + j * DCORE_DEC_OFFSET;  in gaudi2_get_decoder_idle_status()
7556 			dcore_vdec_id + DCORE_OFFSET * dcore_id;  in gaudi2_mmu_vdec_dcore_prepare()
7579 	u32 dcore_offset = dcore_id * DCORE_OFFSET;  in gaudi2_mmu_dcore_prepare()
8214 				dcore_id * DCORE_OFFSET +  in gaudi2_ack_module_razwi_event_handler()
8486 				(index / NUM_OF_TPC_PER_DCORE) * DCORE_OFFSET +  in gaudi2_handle_qm_sei_err()
8501 		qman_base = mmDCORE0_MME_QM_BASE + index * DCORE_OFFSET;  in gaudi2_handle_qm_sei_err()
8761 				DCORE_OFFSET * (dec_index / NUM_OF_DEC_PER_DCORE) +  in gaudi2_handle_dec_err()
8795 	sts_addr = mmDCORE0_MME_CTRL_LO_INTR_CAUSE + DCORE_OFFSET * mme_index;  in gaudi2_handle_mme_err()
8796 	sts_clr_addr = mmDCORE0_MME_CTRL_LO_INTR_CLEAR + DCORE_OFFSET * mme_index;  in gaudi2_handle_mme_err()
8838 	sts_addr = mmDCORE0_MME_ACC_INTR_CAUSE + DCORE_OFFSET * mme_index;  in gaudi2_handle_mme_wap_err()
8839 	sts_clr_addr = mmDCORE0_MME_ACC_INTR_CLEAR + DCORE_OFFSET * mme_index;  in gaudi2_handle_mme_wap_err()
9089 	sei_cause_addr = mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE + DCORE_OFFSET * sm_index;  in gaudi2_handle_sm_err()
9090 	cq_intr_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR + DCORE_OFFSET * sm_index;  in gaudi2_handle_sm_err()
9227 	return mmDCORE0_HMMU0_MMU_BASE + dcore * DCORE_OFFSET + index_in_dcore * DCORE_HMMU_OFFSET;  in get_hmmu_base()
10359 			u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;  in gaudi2_memset_device_memory()
10416 			u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;  in gaudi2_memset_device_memory()
10514 	cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10515 	cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10516 	cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10517 	cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10518 	cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10519 	cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10530 		cq_lbw_l_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10531 		cq_lbw_h_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10532 		cq_lbw_data_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10533 		cq_base_l_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10534 		cq_base_h_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10535 		cq_size_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10549 	mon_sts_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10550 	mon_cfg_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10556 		mon_sts_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10557 		mon_cfg_addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10569 	addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
10574 		addr += DCORE_OFFSET;  in gaudi2_restore_user_sm_registers()
11211 		base = mmDCORE0_DEC0_CMD_BASE + dcore_id * DCORE_OFFSET +  in gaudi2_get_dec_base_addr()